Register-transfer level (RTL) is the abstraction at which digital chips are designed. Rather than drawing individual transistors or gates, an engineer describes the circuit as a set of registers that hold state and the combinational logic that computes each register's next value, with everything advancing on the edge of a clock. This description is written in a hardware description language such as Verilog, SystemVerilog, or VHDL, and it is the golden model that a design is simulated, verified, and signed off against before any gates exist. Synthesis then compiles the RTL into a physical gate-level netlist.\n\nRTL captures behavior as state plus logic, timed by a clock. The mental model is simple: registers (flip-flops) remember values, and between them sit clouds of combinational logic that transform those values. On each rising clock edge every register latches the result the logic computed during the cycle, so a design is a network of register-to-register paths. Writing at this level lets an engineer specify what the hardware does each cycle without hand-placing gates, which is why RTL, not schematics, has been the entry point for essentially all large digital design since the 1990s. The clock period must be long enough for the slowest logic path between two registers to settle.\n\nIt is a language and a synthesizable subset, not free-form code. RTL is expressed in an HDL, but only a subset of the language actually maps to hardware. Constructs like clocked always-blocks, continuous assignments, and case statements describe real registers and multiplexers; other constructs (delays, file I/O, unbounded loops) exist only for the testbench that stimulates and checks the design in simulation. Verilog and its superset SystemVerilog dominate in industry, with VHDL common in aerospace and Europe. Discipline about the synthesizable subset is what keeps the simulated behavior and the synthesized silicon identical — the whole point of designing at RTL.\n\n| Level | What you describe | Example |\n|---|---|---|\n| Behavioral | the algorithm, untimed | a C-like model |\n| RTL | registers + logic per clock | Verilog always-block |\n| Gate netlist | interconnected cells | AND, MUX, flip-flop |\n| Transistor/layout | physical devices, masks | standard-cell layout |\n| Verified at | RTL (the golden source) | simulation, assertions |\n| Compiled by | synthesis → netlist | Design Compiler, Genus |\n\n``svg\n\n``\n\nRTL is the contract the rest of the flow depends on. Because it is the level at which function is defined and verified, RTL sits at the top of the implementation flow: synthesis turns it into gates, place-and-route gives those gates physical locations and wires, static timing analysis checks that every register-to-register path meets the clock, and design-for-test adds structures to screen manufactured parts. Bugs are far cheaper to fix in RTL than after layout, so enormous effort goes into RTL verification — simulation, assertions, coverage, and formal methods. The same RTL can target different process nodes or even FPGAs, which is why it is both the design's source of truth and its portability layer.\n\nRead RTL through a quant lens rather than a 'code for chips' lens: the number it governs is the clock period, set by the worst-case combinational delay between any two registers, so every design choice is really a bet about how much logic fits in one cycle. Add logic to a path and you either slow the clock or must pipeline by inserting another register; that register-to-register delay budget is what synthesis, placement, and timing analysis all spend their effort meeting. Designing at RTL means reasoning in registers-per-cycle rather than transistors, trading a small loss of hand-tuned density for the ability to describe, verify, and re-target billions of gates.