Heterogeneous Computing with OpenCL is the programming framework for writing portable parallel applications that execute across diverse hardware accelerators — CPUs, GPUs, FPGAs, and DSPs — using a unified host-device model where compute kernels are compiled at runtime for the target device, enabling a single codebase to leverage whatever parallel hardware is available.

OpenCL (Open Computing Language) was created to solve the portability problem: CUDA runs only on NVIDIA GPUs, while real-world systems contain diverse accelerators. OpenCL provides a vendor-neutral programming model supported across AMD, Intel, NVIDIA, ARM, Xilinx/AMD FPGAs, and other devices.

OpenCL Architecture:

Memory Model: OpenCL defines four memory spaces: global (device DRAM, accessible by all work-items), local (per-work-group scratchpad, like CUDA shared memory), private (per-work-item registers), and constant (read-only global, cached). The programmer explicitly manages data movement between host and device memory using clEnqueueReadBuffer/clEnqueueWriteBuffer, or uses Shared Virtual Memory (SVM) for unified addressing.

Runtime Compilation: OpenCL kernels are compiled at runtime from source (OpenCL C/C++) or from SPIR-V intermediate representation. This enables: device-specific optimization (the driver compiler generates optimal code for the actual target), portability (same kernel runs on GPU or FPGA with appropriate compilation), and dynamic kernel generation (host code can construct kernel source strings at runtime). The trade-off is first-run compilation latency (mitigated by program caching).

Performance Portability Challenges: Despite source portability, achieving performance portability is difficult. Optimal work-group sizes, vector widths, memory access patterns, and tiling strategies differ dramatically between GPUs (want thousands of work-items, coalesced access) and CPUs (want few work-groups with SIMD vectorization). Libraries like SYCL, Kokkos, and RAJA add abstraction layers that adapt execution strategies per device.

FPGA Execution: OpenCL for FPGAs (Intel/Xilinx) represents a fundamentally different execution model: instead of launching work-items on fixed compute units, the OpenCL compiler synthesizes a custom hardware pipeline from the kernel. The "compilation" takes hours (hardware synthesis) but the resulting circuit can achieve order-of-magnitude energy efficiency for specific workloads. Pipeline parallelism replaces data parallelism as the primary performance mechanism.

Heterogeneous computing with OpenCL embodies the principle that no single processor type is optimal for all workloads — by providing a portable framework for harnessing diverse accelerators, OpenCL enables applications to leverage the right hardware for each computational pattern, a capability that becomes increasingly critical as hardware specialization accelerates.