High-NA EUV lithography is the next-generation patterning system that increases the numerical aperture of the EUV projection optics from 0.33 to 0.55 — shrinking the minimum printable half-pitch from ~13 nm to ~8 nm in a single exposure. ASML's EXE:5000 (first shipment 2024, ~€350M per tool) is the only High-NA scanner; Intel is the lead customer (Intel 14A, ~2026), with TSMC and Samsung following. High-NA extends EUV lithography one or two more nodes beyond what current 0.33-NA systems can resolve, pushing the industry toward angstrom-scale patterning without falling back to costly multi-patterning.

Resolution — Rayleigh's equation. The minimum resolvable half-pitch (HP) in optical lithography:

For current EUV ($\lambda$ = 13.5 nm, NA = 0.33, $k_1$ ≈ 0.3–0.4): HP ≈ 12–16 nm. For High-NA ($\lambda$ = 13.5 nm, NA = 0.55, $k_1$ ≈ 0.3–0.4): HP ≈ 7–10 nm. The 67% increase in NA delivers a proportional improvement in resolution — the same physics that drives microscope objectives, now at 13.5 nm wavelength with all-reflective optics in vacuum.

Depth of focus — the trade-off. Increasing NA narrows depth of focus (DoF):

At 0.55 NA: DoF drops by $(0.55/0.33)^2 \approx 2.8\times$ compared to 0.33 NA — from ~100 nm to ~35–45 nm. This razor-thin focus budget demands: (1) flatter wafers (global planarity <10 nm), (2) ultra-precise wafer stage leveling (real-time topography correction), (3) thinner resist stacks (~20–30 nm), and (4) tighter CMP uniformity across every underlayer.

Anamorphic optics — the enabling innovation. Simply scaling a 0.33-NA lens to 0.55 NA would require mirrors too large to manufacture. ASML's solution: an anamorphic (non-rotationally-symmetric) optical design that magnifies 4× in one axis and 8× in the perpendicular axis. This keeps mirror sizes manageable but means the mask field shrinks from 26×33 mm (standard EUV) to 26×16.5 mm in the scanning direction — exactly half the field area. Consequence: die sizes larger than 26×16.5 mm require field stitching (two exposures bonded at the overlap), which adds complexity and edge-placement error at the stitch boundary.

The half-field problem. Because the exposure field is halved in one dimension, any chip larger than ~26×16.5 mm must be exposed in two stitched shots. For AI accelerators (H100 die = 814 mm², MI300X chiplet = ~700 mm²), this means either: (a) redesigning the chip to fit within the half-field (costly), (b) stitching with sub-1 nm overlay accuracy (challenging), or (c) using High-NA only for the most critical layers (metal/via pitches below ~20 nm) while keeping the rest on 0.33-NA EUV or immersion (the expected initial approach).

Resist challenges. Thinner resist (~20–25 nm) with reduced photon shot noise requires higher EUV dose — but EUV source power is finite, so throughput degrades without mitigation. Metal-oxide resists (MOx, e.g. tin-oxide-based inorganic resists) offer 2–3× better EUV absorption than chemically-amplified resists (CAR) at the same thickness, enabling adequate dose at production throughput. Dry-development resists (no wet puddle) reduce pattern collapse in the high-aspect-ratio features that thin resist creates.

Source power. Current EUV sources deliver 250–500 W of in-band 13.5 nm power to the intermediate focus. High-NA needs 500–800 W to maintain throughput at the higher dose demanded by thinner resist and finer features. ASML/Trumpf's tin-droplet laser-produced-plasma (LPP) source is being scaled with higher-repetition-rate CO₂ lasers (~100 kHz) and optimized tin-droplet targeting. Reaching 800 W in-band is the critical path item for High-NA productivity parity with 0.33-NA tools.

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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">High-NA EUV — The Next Lithography Frontier</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">NA 0.55 (vs 0.33): doubles resolution to ~8 nm half-pitch — enabling 2nm and beyond without multi-patterning</text>

  <!-- === TOP: Optical comparison === -->
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  <text x="380" y="82" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">EUV vs High-NA EUV Optics</text>

  <!-- Standard EUV -->
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  <text x="190" y="112" fill="#93c5fd" font-size="9" text-anchor="middle" font-weight="600">Current EUV (NA = 0.33)</text>
  <text x="190" y="128" fill="#8b98a5" font-size="8.5" text-anchor="middle">Resolution: k₁λ/NA = 13 nm half-pitch</text>
  <text x="190" y="144" fill="#8b98a5" font-size="8.5" text-anchor="middle">Wavelength: 13.5 nm | 250W source</text>
  <text x="190" y="160" fill="#8b98a5" font-size="8.5" text-anchor="middle">Magnification: 4× | Field: 26×33 mm</text>
  <text x="190" y="172" fill="#6b7684" font-size="7.5" text-anchor="middle">ASML NXE:3800E (production workhorse)</text>

  <!-- High-NA EUV -->
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  <text x="515" y="112" fill="#6ee7b7" font-size="9" text-anchor="middle" font-weight="600">High-NA EUV (NA = 0.55)</text>
  <text x="515" y="128" fill="#8b98a5" font-size="8.5" text-anchor="middle">Resolution: k₁λ/NA = 8 nm half-pitch</text>
  <text x="515" y="144" fill="#8b98a5" font-size="8.5" text-anchor="middle">Wavelength: 13.5 nm | 350-500W source</text>
  <text x="515" y="160" fill="#8b98a5" font-size="8.5" text-anchor="middle">Magnification: 4×/8× anamorphic | Field: 26×16.5 mm</text>
  <text x="515" y="172" fill="#6b7684" font-size="7.5" text-anchor="middle">ASML EXE:5000 (first tool at Intel, 2025)</text>

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  <text x="350" y="135" fill="#fbbf24" font-size="14" text-anchor="middle">→</text>

  <!-- === MIDDLE LEFT: Technical changes === -->
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  <text x="200" y="213" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Key Technical Changes</text>

  <text x="45" y="235" fill="#34d399" font-size="8.5" font-weight="600">Anamorphic optics (4×/8×)</text>
  <text x="45" y="251" fill="#8b98a5" font-size="8.5">different magnification in X vs Y → 8× in scan</text>
  <text x="45" y="269" fill="#60a5fa" font-size="8.5" font-weight="600">Half-field exposure</text>
  <text x="45" y="285" fill="#8b98a5" font-size="8.5">26×16.5 mm (half of standard) → stitching needed</text>
  <text x="45" y="303" fill="#fbbf24" font-size="8.5" font-weight="600">Larger mirrors + source power</text>
  <text x="45" y="315" fill="#8b98a5" font-size="8.5">mirrors up to 1m diameter, &gt; 350W EUV power</text>

  <!-- === MIDDLE RIGHT: Challenges === -->
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  <text x="562" y="213" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Challenges and Tradeoffs</text>

  <text x="410" y="235" fill="#f87171" font-size="8.5" font-weight="600">Reduced depth of focus</text>
  <text x="410" y="251" fill="#8b98a5" font-size="8.5">DOF ∝ λ/NA² → thinner resist, tighter flatness</text>
  <text x="410" y="269" fill="#fbbf24" font-size="8.5" font-weight="600">Half-field stitching</text>
  <text x="410" y="285" fill="#8b98a5" font-size="8.5">large dies need 2 exposures → overlay at stitch</text>
  <text x="410" y="303" fill="#60a5fa" font-size="8.5" font-weight="600">Cost: ~$350-400M per tool</text>
  <text x="410" y="315" fill="#8b98a5" font-size="8.5">2× cost of standard EUV ($150-180M)</text>

  <!-- === BOTTOM: Roadmap === -->
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  <text x="380" y="343" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">EUV Lithography Roadmap</text>

  <text x="100" y="367" fill="#8b98a5" font-size="9" text-anchor="middle" font-weight="600">193i (NA 1.35)</text>
  <text x="100" y="381" fill="#8b98a5" font-size="8" text-anchor="middle">≥ 7nm node</text>
  <text x="100" y="393" fill="#6b7684" font-size="7.5" text-anchor="middle">+ multi-patterning</text>

  <text x="260" y="367" fill="#60a5fa" font-size="9" text-anchor="middle" font-weight="600">EUV (NA 0.33)</text>
  <text x="260" y="381" fill="#8b98a5" font-size="8" text-anchor="middle">7nm → 3nm</text>
  <text x="260" y="393" fill="#6b7684" font-size="7.5" text-anchor="middle">single-pattern to 13nm HP</text>

  <text x="420" y="367" fill="#34d399" font-size="9" text-anchor="middle" font-weight="600">High-NA (NA 0.55)</text>
  <text x="420" y="381" fill="#8b98a5" font-size="8" text-anchor="middle">2nm → A14</text>
  <text x="420" y="393" fill="#6b7684" font-size="7.5" text-anchor="middle">single-pattern to 8nm HP</text>

  <text x="580" y="367" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">Hyper-NA? (NA 0.75)</text>
  <text x="580" y="381" fill="#8b98a5" font-size="8" text-anchor="middle">research phase</text>
  <text x="580" y="393" fill="#6b7684" font-size="7.5" text-anchor="middle">sub-5nm HP (2030s?)</text>

  <text x="700" y="367" fill="#f87171" font-size="9" text-anchor="middle" font-weight="600">Post-EUV?</text>
  <text x="700" y="381" fill="#8b98a5" font-size="8" text-anchor="middle">e-beam, DSA</text>
  <text x="700" y="393" fill="#6b7684" font-size="7.5" text-anchor="middle">nanoimprint</text>

  <!-- Key insight -->
  <rect x="25" y="411" width="710" height="22" rx="3" fill="#0b1220" stroke="#233043" stroke-width="0.8"/>
  <text x="380" y="426" fill="#fbbf24" font-size="9" text-anchor="middle">High-NA extends EUV's single-patterning limit by ~1.7× — delaying the return to expensive multi-patterning.</text>

  <text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">High-NA EUV is a $400M bet that optics can keep scaling — ASML is the only company on Earth that builds these machines.</text>
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Economics — the $350M question. A single EXE:5000 costs roughly €350M — nearly twice the NXE:3800 (€180M). To justify the investment, each High-NA tool must process enough wafers at enough layers to amortize its cost over production volume. Intel's calculus: High-NA eliminates the need for EUV double-patterning (which uses two 0.33-NA exposures per layer), so one High-NA shot replaces two 0.33-NA shots at critical metal layers — effectively doubling the throughput per critical layer and justifying the tool premium. The break-even requires High-NA throughput to reach at least 150 WPH (wafers per hour) at production dose.

What High-NA means for AI chip manufacturing. The tightest metal pitches on next-generation AI accelerators (18–20 nm M1 pitch at Intel 14A / TSMC A14) are below what 0.33-NA EUV can resolve in a single exposure. Without High-NA, these layers would require EUV double-patterning — doubling litho cost and halving effective throughput at the most expensive process step. High-NA makes single-exposure patterning at 8–10 nm half-pitch practical, keeping Moore's Law cost scaling alive for the transistor-dense accelerator dies that power frontier AI training.