High-κ metal gate (HKMG) replaces traditional SiO₂/polysilicon gate stack with high dielectric constant insulator and metal gate electrode, enabling continued transistor scaling below 45nm. Problem solved: SiO₂ gate oxide below ~1.2nm thickness caused excessive tunneling leakage current (exponential increase with thinning). High-κ dielectric: (1) Material—HfO₂ (hafnium dioxide) is industry standard, κ ≈ 25 vs. SiO₂ κ ≈ 3.9; (2) Benefit—thicker physical oxide maintains same capacitance (equivalent oxide thickness, EOT) while dramatically reducing tunneling leakage; (3) EOT—effective SiO₂ thickness, modern HKMG achieves EOT < 0.8nm; (4) Interface layer—thin SiO₂ (0.3-0.5nm) between Si channel and HfO₂ for interface quality. Metal gate: (1) Why—polysilicon suffers depletion effect adding ~0.3nm to EOT, and Fermi level pinning with high-κ; (2) Materials—TiN, TaN, TiAl for work function tuning; (3) NMOS vs. PMOS—different metal stacks set appropriate threshold voltage. Integration schemes: (1) Gate-first—deposit HKMG before source/drain processing (simpler but thermal budget constraints); (2) Gate-last (replacement metal gate)—form dummy poly gate, complete S/D, remove dummy, deposit HKMG (better control, industry standard). Fabrication challenges: achieving target EOT, reliability (PBTI/NBTI with high-κ), threshold voltage control, metal fill in high aspect ratio structures. Impact: HKMG enabled 45nm-to-present scaling, ~1000× leakage reduction vs. equivalent SiO₂. Every advanced logic and memory technology now uses HKMG as the standard gate stack.