High-Level Synthesis (HLS) is the automated transformation of untimed algorithmic descriptions written in C, C++, or SystemC into synthesizable RTL hardware (Verilog/VHDL) — raising the design abstraction level from cycle-accurate register-transfer logic to functional algorithm description, potentially reducing design time by 5-10x for datapath-intensive blocks while the synthesis tool handles scheduling, resource allocation, and interface generation.
HLS Flow
1. C/C++ Algorithm: Write function describing the computation (no hardware concepts). 2. Directives/Pragmas: Annotate with constraints — target clock, pipeline stages, array partitioning. 3. HLS Synthesis: Tool schedules operations, allocates hardware resources, generates FSM. 4. RTL Output: Verilog/VHDL module with clock, reset, handshake interfaces. 5. Verification: Compare RTL simulation output with C functional model (co-simulation). 6. Integration: Generated RTL integrated into SoC like any other block.
What HLS Does Automatically
| Task | HLS Automation |
|---|---|
| Scheduling | Assign operations to clock cycles based on timing |
| Resource Allocation | Map operations to hardware (adders, multipliers, memories) |
| Resource Sharing | Reuse hardware across different clock cycles |
| Pipelining | Insert pipeline stages with specified initiation interval |
| Interface Synthesis | Generate AXI, FIFO, handshake, or memory interfaces |
| Memory Architecture | Map arrays to SRAM, registers, or distributed memory |
| Loop Optimization | Unroll, pipeline, flatten loops based on directives |
HLS Tools
| Tool | Vendor | Input Languages | Target |
|---|---|---|---|
| Vitis HLS (Vivado HLS) | AMD/Xilinx | C/C++, OpenCL | FPGA (primary), ASIC |
| Catapult HLS | Siemens EDA | C/C++, SystemC | ASIC, FPGA |
| Stratus HLS | Cadence | SystemC, C++ | ASIC |
| Bambu | Open-source | C/C++ | FPGA, ASIC |
Key HLS Directives (Vitis HLS Example)
void matrix_mul(int A[N][N], int B[N][N], int C[N][N]) {
#pragma HLS PIPELINE II=1
#pragma HLS ARRAY_PARTITION variable=A complete dim=2
#pragma HLS ARRAY_PARTITION variable=B complete dim=1
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++)
sum += A[i][k] * B[k][j];
C[i][j] = sum;
}
}
HLS Strengths and Limitations
| Strength | Limitation |
|---|---|
| 5-10x faster design cycle | Generated RTL 10-30% less efficient than hand-coded |
| Easy design space exploration | Complex control logic hard to express in C |
| Algorithm portability (C testbench) | Timing-critical designs still need hand RTL |
| Excellent for datapath/DSP | Not suitable for full SoC design |
Where HLS Excels
- Image/video processing pipelines.
- DSP algorithms (FFT, filters, convolution).
- Neural network accelerators (convolution, matrix multiply).
- Packet processing and networking.
- FPGA accelerators (rapid development cycle).
High-level synthesis is transforming hardware design productivity — by enabling algorithm designers to create hardware without mastering RTL, HLS dramatically accelerates the development of application-specific accelerators, making custom hardware accessible to a broader engineering community and reducing the time from algorithm to silicon.
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.