Holding voltage is the sustained voltage across an ESD protection clamp after it triggers and enters snapback — the critical parameter that determines whether the clamp safely turns off after an ESD event or latches into a destructive sustained conduction state that shorts the power supply.

What Is Holding Voltage?

• Definition: The voltage (Vh) at which an ESD protection device operates in its low-impedance on-state after snapback, where the device sustains current flow with minimal voltage drop to efficiently dissipate ESD energy.
• Snapback Behavior: When a GGNMOS or SCR triggers, the voltage initially rises to Vt1, then "snaps back" to a much lower voltage Vh as the parasitic bipolar transistor fully turns on.
• Power Dissipation: During the ESD event, the clamp dissipates P = Vh × I_ESD — lower Vh means less power dissipation in the clamp and better energy handling.
• Latchup Boundary: Vh defines the critical boundary between safe ESD operation and dangerous latchup — if Vh < VDD, the power supply sustains current through the clamp after the ESD event ends.

Why Holding Voltage Matters

• Latchup Prevention: The most dangerous failure mode — if Vh drops below VDD, the external power supply provides enough voltage to keep the clamp conducting after the ESD transient. This sustained current can melt metal interconnects, destroy the clamp, or cause chip-level thermal runaway.
• Latchup Margin: Industry practice requires Vh > VDD + 10% margin minimum. For automotive applications, Vh > 1.5 × VDD is often required.
• ESD Efficiency: Lower Vh during the ESD pulse means less energy dissipated in the clamp and more current handling capability for a given device size.
• SCR Challenge: Silicon Controlled Rectifiers have extremely low Vh (~1.5V) which provides excellent ESD efficiency but creates severe latchup risk for designs with VDD > 1.2V.
• Temperature Effects: Holding voltage typically decreases at elevated temperature, making high-temperature operation the worst case for latchup margin.

Holding Voltage by Device Type

Design Techniques for Holding Voltage Control

• Ballast Resistance: Adding non-silicided drain regions increases the effective Vh by adding resistance in the current path — the most common technique for GGNMOS latchup immunity.
• Segmented SCR: Breaking a large SCR into smaller segments with added resistance between segments raises the effective Vh while maintaining good ESD current capacity.
• Well Engineering: Modifying N-well and P-well doping profiles changes the parasitic bipolar transistor gain, directly affecting Vh.
• Cascode Stacking: Stacking two devices in series doubles the effective Vh, suitable for high-VDD applications (3.3V, 5V I/O).
• Gate Coupling: Applying a small gate bias to GGNMOS clamps can shift the snapback characteristics and increase Vh.

Latchup Testing and Verification

• JEDEC JESD78: Standard latchup test applying ±100 mA at each I/O pin and ±VDD × 1.5 at supply pins, verifying the chip recovers without sustained excess current.
• TLP Characterization: Maps the complete I-V curve including Vh to verify latchup margin across temperature corners.
• Transient Simulation: SPICE simulation with foundry ESD models verifies Vh under all operating conditions and process corners.

Holding voltage is the parameter that separates a safe ESD event from a catastrophic latchup failure — ensuring Vh remains above VDD across all process, voltage, and temperature corners is one of the most critical requirements in ESD protection design.