Hydrogen Anneal for Interface Passivation is the post-deposition thermal treatment in H₂-containing ambient (typically 450-550°C in H₂/N₂ forming gas) — allowing hydrogen to diffuse through the dielectric and passivate dangling Si bonds at the Si/SiO₂ or Si/high-k interface — reducing interface trap density (Dit) and improving device reliability and performance by 10-30%. Hydrogen annealing is essential for interface quality at all nodes.
Forming Gas Anneal (FGA) Process
FGA uses a gas mixture of H₂ (5-10%) and N₂ (balance), heated to 400-550°C in a furnace or rapid thermal anneal (RTA) chamber. Hydrogen diffuses through the oxide from the gas phase, reaching the Si interface where it bonds to "dangling" Si atoms (Si•, unpaired electrons). The Si-H bonds are stable at room temperature (Si-H bond energy ~3.6 eV), passivating the trap. FGA is typically performed after high-k deposition and metal gate formation (post-gate anneal), as final process step before contact patterning.
Interface State Density Reduction
Si/SiO₂ interface naturally has ~10¹¹-10¹² cm⁻² eV⁻¹ trap states (Dit) due to: (1) dangling Si bonds (Pb centers), (2) oxygen vacancies, (3) strain-induced defects. FGA reduces Dit by 1-2 orders of magnitude, to ~10⁹-10¹⁰ cm⁻² eV⁻¹, by passivating Pb centers. Lower Dit improves: (1) subthreshold swing (SS) — better electrostatic control via lower charge in interface states, (2) leakage — fewer trap-assisted tunneling paths, and (3) 1/f noise — fewer scattering centers.
Hydrogen Diffusion Through Oxide and Nitride
Hydrogen is the smallest atom and diffuses rapidly through SiO₂ even at modest temperature. Diffusion coefficient of H in SiO₂ is ~10⁻¹² cm²/s at 450°C, enabling >100 nm diffusion depth in minutes. However, diffusion through SiN is much slower (~10⁻¹⁶ cm²/s at 450°C), creating a barrier. For Si/SiN interfaces, hydrogen passivation is limited unless anneal temperature is elevated (>550°C, risking other damage). This is why FGA is most effective immediately after oxide deposition (before SiN spacer) or after high-k gate dielectric (before metal cap).
Alloy Anneal for Ohmic Contacts
For ohmic contacts (metal/semiconductor interface), hydrogen anneal improves contact resistance by passivating interface states and reducing tunneling barrier height. H₂ anneal at elevated temperature (>500°C) in contact formation steps (after metal deposition on doped semiconductor) reduces contact resistance by 20-50%. This is used extensively in power devices (SiC Schottky diodes, GaN HEMTs) and advanced CMOS contacts.
Hydrogen-Induced Damage in High-k/Metal Gate Stacks
While hydrogen passivates Si interface states, it can damage high-k dielectrics and metal electrodes: (1) hydrogen can become trapped in HfO₂, increasing leakage (trapping sites), (2) hydrogen can form H₂O at the HfO₂/metal interface, degrading interface quality, and (3) hydrogen can reduce oxide (HfO₂ → Hf + H₂O), introducing oxygen vacancies. For high-k/metal gate stacks, FGA temperature and duration are carefully optimized (lower temperature, shorter time) to passivate Si interface states without damaging high-k. Typical FGA for high-k is 300-400°C for 30 min (vs 450°C for 20 min for SiO₂).
Alternatives: Deuterium and Other Passivation
Deuterium (D, heavy H) exhibits slower diffusion (kinetic isotope effect: D diffuses ~√2 slower than H) and forms stronger D-Si bonds (1-2% stronger). Deuterium annealing (DA) shows improved stability vs FGA: PBTI/NBTI drift is reduced ~10% due to slower depassivation kinetics. However, deuterium is more expensive and requires specialized gas handling. DA is used in high-reliability applications (automotive, aerospace) despite cost premium.
Repassivation and Reliability Trade-off
During device operation at elevated temperature (85°C = 358 K), hydrogen can depassivate (reverse reaction: Si-H → Si• + H). Depassivation rate depends on temperature and electric field (hot carrier injection accelerates it). This causes Vt drift over years of operation (PBTI/NBTI reliability concern). Lower FGA temperature (preserving H concentration) delays repassivation but risks incomplete initial passivation. Typical NBTI Vt shift is 20-50 mV over 10 years of continuous stress at 85°C.
Interface Passivation at Multiple Interfaces
Modern devices have multiple interfaces requiring passivation: (1) Si/SiO₂ (channel bottom in planar CMOS), (2) Si/high-k (FinFET channel in contact with HfO₂), (3) S/D junction/contact (metal/Si or metal/doped Si). FGA is optimized differently for each: Si/high-k requires lower temperature to avoid high-k damage, while S/D junction anneal can be higher temperature. Multi-step annealing (different temperatures for different interfaces) is sometimes used.
Process Integration Challenges
FGA timing is critical: too early (before spacer/isolation complete) introduces hydrogen that damages structures or causes hydrogen-induced defects; too late (after metal cap) blocks hydrogen diffusion from reaching Si interface. FGA is typically final anneal step in gate/dielectric module, just before contact patterning, but after all gate structure formation. Temperature overshoot must be avoided (risks dopant diffusion, metal migration, stress relaxation).
Summary
Hydrogen annealing is a transformative process, improving interface quality and enabling reliable advanced CMOS. Ongoing challenges in balancing H passivation with damage mitigation and long-term stability drive continued research into FGA optimization and alternative passivation approaches.