<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">MOSFET: a voltage on the gate opens a channel between source and drain</text><text x="20" y="50" fill="#8b949e" font-size="12.5">The four-terminal switch behind every logic gate — and the three regions it operates in</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 · The structure</text><text x="32" y="106" fill="#8b949e" font-size="10.5">n-channel MOSFET cross-section</text><!-- terminals --><text x="60" y="132" fill="#9fd8ef" font-size="10.5" font-weight="700">S</text><text x="128" y="132" fill="#e0b13a" font-size="10.5" font-weight="700">G</text><text x="196" y="132" fill="#9fd8ef" font-size="10.5" font-weight="700">D</text><line x1="63" y1="138" x2="63" y2="176" stroke="#6f8fb0" stroke-width="2"/><line x1="131" y1="138" x2="131" y2="158" stroke="#d08a4a" stroke-width="2"/><line x1="199" y1="138" x2="199" y2="176" stroke="#6f8fb0" stroke-width="2"/><!-- substrate --><rect x="40" y="176" width="182" height="118" rx="3" fill="#1c2733" stroke="#233041"/><text x="132" y="284" fill="#8b949e" font-size="9.5" text-anchor="middle">p-type body (substrate)</text><!-- source / drain --><rect x="46" y="176" width="46" height="52" rx="2" fill="#38506a"/><text x="69" y="206" fill="#cfe4f5" font-size="9.5" text-anchor="middle">n+</text><rect x="170" y="176" width="46" height="52" rx="2" fill="#38506a"/><text x="193" y="206" fill="#cfe4f5" font-size="9.5" text-anchor="middle">n+</text><!-- gate oxide + gate --><rect x="92" y="170" width="78" height="6" fill="#f0d9b5"/><rect x="92" y="158" width="78" height="12" rx="2" fill="#d08a4a"/><text x="131" y="152" fill="#f0d9b5" font-size="8" text-anchor="middle">gate</text><text x="176" y="168" fill="#f0d9b5" font-size="7.5">oxide</text><!-- channel --><rect x="92" y="176" width="78" height="7" fill="#34d399" opacity="0.85"/><text x="131" y="196" fill="#7ee6c0" font-size="8.5" text-anchor="middle">inversion channel</text><line x1="98" y1="200" x2="164" y2="200" stroke="#34d399" stroke-width="1.4" marker-end="url(#ar)"/><text x="131" y="243" fill="#8b949e" font-size="8.5" text-anchor="middle">electrons drift S → D</text><text x="32" y="316" fill="#adb5bd" font-size="10">V <tspan font-size="7" dy="2">GS</tspan><tspan dy="-2"> pulls electrons up to form a thin</tspan></text><text x="32" y="332" fill="#adb5bd" font-size="10">conducting layer under the oxide. No</text><text x="32" y="348" fill="#adb5bd" font-size="10">gate voltage → no channel → no current.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 · Three regions</text><text x="279" y="106" fill="#8b949e" font-size="10.5">drain current vs V<tspan font-size="7" dy="2">DS</tspan></text><!-- axes --><line x1="300" y1="128" x2="300" y2="300" stroke="#8b949e" stroke-width="1.2"/><line x1="300" y1="300" x2="478" y2="300" stroke="#8b949e" stroke-width="1.2"/><text x="292" y="126" fill="#8b949e" font-size="8.5" text-anchor="end">I<tspan font-size="6" dy="2">D</tspan></text><text x="478" y="316" fill="#8b949e" font-size="8.5" text-anchor="end">V<tspan font-size="6" dy="2">DS</tspan></text><!-- saturation boundary --><path d="M300 300 Q345 150 470 138" fill="none" stroke="#6b5fb0" stroke-width="1.1" stroke-dasharray="3 3"/><text x="404" y="150" fill="#a99cf0" font-size="8">V<tspan font-size="6" dy="2">DS</tspan><tspan dy="-2">=V</tspan><tspan font-size="6" dy="2">GS</tspan><tspan dy="-2">−V</tspan><tspan font-size="6" dy="2">th</tspan></text><!-- three curves increasing VGS --><path d="M300 300 Q322 250 340 244 L470 240" fill="none" stroke="#34d399" stroke-width="1.8"/><path d="M300 300 Q332 214 356 206 L470 202" fill="none" stroke="#34d399" stroke-width="1.8"/><path d="M300 300 Q344 176 372 166 L470 162" fill="none" stroke="#34d399" stroke-width="1.8"/><text x="474" y="164" fill="#7ee6c0" font-size="8" text-anchor="start">V<tspan font-size="6" dy="2">GS</tspan><tspan dy="-2">↑</tspan></text><!-- region labels --><text x="318" y="286" fill="#e0b13a" font-size="8.5">triode</text><text x="420" y="188" fill="#e0b13a" font-size="8.5">saturation</text><text x="330" y="296" fill="#f87171" font-size="8" text-anchor="middle"></text><circle cx="300" cy="300" r="2.4" fill="#f87171"/><text x="306" y="296" fill="#f87171" font-size="8">cutoff</text><text x="279" y="330" fill="#adb5bd" font-size="9.5">Triode: acts like a V-controlled resistor.</text><text x="279" y="345" fill="#adb5bd" font-size="9.5">Saturation: current flattens → used for gain.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 · What sets the current</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the knobs designers actually turn</text><rect x="526" y="118" width="202" height="40" rx="4" fill="#111a24" stroke="#30363d"/><text x="536" y="134" fill="#7ee6c0" font-size="9" font-weight="700">Saturation current</text><text x="536" y="150" fill="#e6edf3" font-size="9.5">I<tspan font-size="6.5" dy="2">D</tspan><tspan dy="-2"> = ½·µC</tspan><tspan font-size="6.5" dy="2">ox</tspan><tspan dy="-2">·(W/L)·(V</tspan><tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2">−V</tspan><tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2">)²</tspan></text><!-- knob bars --><text x="526" y="180" fill="#adb5bd" font-size="9.5">overdrive V<tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2">−V</tspan><tspan font-size="6.5" dy="2">th</tspan></text><rect x="526" y="186" width="202" height="7" rx="3" fill="#161f2b"/><rect x="526" y="186" width="180" height="7" rx="3" fill="#34d399"/><text x="526" y="210" fill="#adb5bd" font-size="9.5">aspect ratio W/L</text><rect x="526" y="216" width="202" height="7" rx="3" fill="#161f2b"/><rect x="526" y="216" width="146" height="7" rx="3" fill="#38bdf8"/><text x="526" y="240" fill="#adb5bd" font-size="9.5">mobility × oxide cap µC<tspan font-size="6.5" dy="2">ox</tspan></text><rect x="526" y="246" width="202" height="7" rx="3" fill="#161f2b"/><rect x="526" y="246" width="120" height="7" rx="3" fill="#a99cf0"/><text x="526" y="278" fill="#8b949e" font-size="9.5">Squared overdrive → a small V<tspan font-size="6.5" dy="2">GS</tspan></text><text x="526" y="293" fill="#8b949e" font-size="9.5">swing gives a large current swing —</text><text x="526" y="308" fill="#8b949e" font-size="9.5">that gain is what makes it a switch</text><text x="526" y="323" fill="#8b949e" font-size="9.5">and an amplifier.</text><text x="526" y="346" fill="#e0913a" font-size="9.5">Short channels break the square law</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#f87171" font-size="11" font-weight="700">Cutoff</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">V<tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2"> < V</tspan><tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2">: channel off. Ideally</tspan></text><text x="32" y="440" fill="#adb5bd" font-size="9.5">zero current — only leakage flows.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#e0b13a" font-size="11" font-weight="700">Triode (linear)</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">V<tspan font-size="6.5" dy="2">DS</tspan><tspan dy="-2"> < V</tspan><tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2">−V</tspan><tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2">: a resistor whose</tspan></text><text x="279" y="440" fill="#adb5bd" font-size="9.5">value the gate voltage sets.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#34d399" font-size="11" font-weight="700">Saturation</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">V<tspan font-size="6.5" dy="2">DS</tspan><tspan dy="-2"> ≥ V</tspan><tspan font-size="6.5" dy="2">GS</tspan><tspan dy="-2">−V</tspan><tspan font-size="6.5" dy="2">th</tspan><tspan dy="-2">: current ~flat.</tspan></text><text x="526" y="440" fill="#adb5bd" font-size="9.5">The region used for logic & gain.</text><defs><marker id="ar" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#34d399"/></marker></defs></svg>
III-V MOSFETs are transistors that use compound semiconductors from groups III and V of the periodic table (InGaAs, InP, GaAs) as the channel material — offering 5-10x higher electron mobility than silicon for potentially faster switching at lower supply voltages in future logic nodes.
Why III-V Materials?
- Electron Mobility Comparison:
- Si: ~500 cm²/V·s
- Strained Si: ~800 cm²/V·s
- In0.53Ga0.47As: ~10,000 cm²/V·s
- InAs: ~30,000 cm²/V·s
- Higher mobility → higher drive current at lower voltage → lower dynamic power.
- At 0.5V supply (vs. 0.7V for Si), III-V channels can match Si current with dramatically lower $CV^2f$ power.
Key III-V Channel Materials
| Material | Electron Mobility | Bandgap | Advantage |
|---|---|---|---|
| In0.53Ga0.47As | ~10,000 cm²/V·s | 0.74 eV | Lattice-matched to InP substrate |
| InAs | ~30,000 cm²/V·s | 0.36 eV | Highest mobility — narrow bandgap limits Vdd |
| GaAs | ~8,500 cm²/V·s | 1.42 eV | Mature technology, good bandgap |
| InP | ~5,400 cm²/V·s | 1.34 eV | Good for RF, wide bandgap |
Integration Challenges
- Lattice Mismatch: InGaAs on Si wafers → high dislocation density. Solutions:
- Graded SiGe/Ge/InGaAs buffer layers.
- Aspect Ratio Trapping (ART) — grow III-V in narrow trenches to confine defects.
- Wafer bonding — bond III-V epi to Si substrate, remove original substrate.
- Interface Quality: III-V/oxide interface has high trap density (Dit > 10¹² cm⁻²eV⁻¹) — requires passivation (Al2O3/InGaAs treatment).
- P-type Challenge: III-V materials have excellent electron mobility but poor hole mobility — PMOS still needs Ge or strained SiGe channels.
Current State
- Intel, imec, TSMC, IBM have demonstrated III-V FinFETs and nanowires at research level.
- Not yet in production — Si/SiGe strain engineering continues to extend silicon to 2nm and beyond.
- Most likely insertion point: III-V NMOS + Ge PMOS co-integrated on Si at sub-1nm equivalent node.
III-V MOSFETs represent the most studied beyond-silicon channel material for high-performance logic — their extraordinary electron mobility makes them a compelling candidate for extending transistor scaling when silicon reaches fundamental velocity limits.
iii-v mosfetcompound semiconductor transistoringaas transistoriii-v cmoshigh mobility channel
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.