Impedance matching. controls how traveling-wave energy transfers among a driver, interconnect, and receiver. When a wave reaches a discontinuity, the reflection coefficient depends on the impedances on the two sides. Open, short, capacitive, inductive, via, connector, package, neck-down, and plane-transition discontinuities all create distinct signatures. Matching does not always mean making source, line, and load numerically identical at every frequency; digital termination is chosen so reflections settle within timing and voltage limits while respecting driver strength, DC power, pin capacitance, and topology. Board engineering turns a logical interconnect into manufactured copper, dielectric, plated holes, solder mask, finishes, and assembled components. Requirements must identify voltage, current, edge rate, loss, jitter, temperature, environment, regulatory class, manufacturable feature sizes, inspection access, service life, and acceptable cost. The electrical reference plane is part of every signal path, so a net cannot be judged from its visible trace alone. Stackup, materials, copper roughness, glass weave, via construction, component launch, connector, enclosure, and cables jointly determine behavior.

Physical principles and design constraints. For a resistive load, the voltage reflection coefficient is Γ = (ZL − Z0) ÷ (ZL + Z0). A positive coefficient raises voltage at the load; a negative coefficient lowers it and reverses the reflected polarity. The source reflection coefficient determines what happens when that energy returns. TDR converts round-trip delay into a spatial impedance profile, but bandwidth, probe launch, fixture, loss, and dispersion limit interpretation. Characteristic impedance follows field geometry and material properties, so trace width alone is insufficient. A 2D or 3D field solver is preferred for dense or unusual cross-sections. High-speed behavior follows electromagnetic fields rather than an ideal wire model. Return current concentrates near the outbound trace at high frequency because that path minimizes loop inductance; discontinuities force fields to spread and create reflection, mode conversion, crosstalk, and radiation. Resistance includes skin and proximity effects, dielectric loss depends on frequency and material, and copper roughness changes effective path length. Power delivery is also distributed: planes, vias, capacitors, packages, and die form a frequency-dependent impedance network with resonances and antiresonances.

Implementation workflow and manufacturing control. Series termination near the source raises effective source impedance and consumes little static power, but the far end initially receives a divided step and settles after reflection. Parallel termination near the receiver absorbs incident energy promptly but draws DC current. Thevenin termination supplies an equivalent resistance to a bias point and consumes static power. AC termination blocks DC but is frequency-dependent and must be tuned. Differential links may use internal receiver termination. Back-drilling and optimized via anti-pads reduce discontinuity rather than terminating it. Multiple loads require topology-aware placement. Implementation begins with an approved stackup and fabrication capability. Constraint classes encode width, spacing, reference layer, impedance, differential gap, length or delay tolerance, via style, neck-down, clearance, and prohibited regions. Placement protects critical current loops before autorouting. Reference changes receive nearby return vias; plane splits are kept away from fast routes; decoupling connects with short, wide paths. Fabrication notes define materials, finished thickness, copper weights, controlled-impedance coupons, via filling, surface finish, solder mask, acceptance criteria, and revision identity.

Applications, alternatives, and system trade-offs. Point-to-point clocks, memory buses, multidrop control nets, RF paths, coaxial connections, SerDes channels, and test fixtures need different solutions. A source-series resistor can work well for one high-impedance receiver but poorly for a branched bus. A parallel resistor can provide clean edges where its power is acceptable. RF networks use broadband or narrowband reactive matching to maximize power or meet noise and stability goals. In all cases, the relevant impedance reference plane and frequency band must be declared; a nominal DC resistance comparison is not sufficient. The right construction depends on the product. Dense compute boards emphasize high layer count, low-loss channels, large BGAs, power delivery, and cooling. Automotive controllers add temperature, vibration, moisture, transient, and long-life requirements. RF boards need field-solver-backed launches and material control. Power boards emphasize creepage, clearance, copper current density, thermal spreading, and switching-loop geometry. Cost-sensitive products minimize layers and via processes, but a lower bare-board price can be erased by yield loss, rework, field returns, or excessive validation cycles.

<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif"><rect width="760" height="470" fill="#0d1117"/><defs><marker id="arrow" viewBox="0 0 10 10" refX="8" refY="5" markerWidth="6" markerHeight="6" orient="auto"><path d="M0 0L10 5L0 10Z" fill="#60a5fa"/></marker><marker id="green" viewBox="0 0 10 10" refX="8" refY="5" markerWidth="6" markerHeight="6" orient="auto"><path d="M0 0L10 5L0 10Z" fill="#34d399"/></marker></defs><text x="380" y="34" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Impedance Matching — Transfer Power Without Reflection</text><text x="380" y="56" fill="#8b98a5" font-size="13" text-anchor="middle">a reactive L-network transforms the load impedance to the source at one design frequency</text><g transform="translate(38 173)"><circle cx="43" cy="43" r="40" fill="#10233b" stroke="#60a5fa" stroke-width="2"/><path d="M20 43q11-20 22 0t22 0" fill="none" stroke="#93c5fd" stroke-width="3"/><text x="43" y="99" fill="#93c5fd" font-size="10" text-anchor="middle">source Zₛ = 50 Ω</text></g><path d="M123 216H217" stroke="#60a5fa" stroke-width="4"/><g transform="translate(217 188)"><path d="M0 28q13-25 26 0t26 0 26 0 26 0" fill="none" stroke="#f59e0b" stroke-width="4"/><text x="52" y="-8" fill="#fbbf24" font-size="10" text-anchor="middle">series L</text></g><path d="M321 216H417" stroke="#60a5fa" stroke-width="4"/><g transform="translate(370 216)"><path d="M0 0v42M-18 42h36M-18 53h36M0 53v49" stroke="#a78bfa" stroke-width="3"/><path d="M-31 102h62M-21 112h42M-11 122h22" stroke="#64748b"/><text x="39" y="60" fill="#c4b5fd" font-size="10">shunt C</text></g><path d="M417 216H484" stroke="#60a5fa" stroke-width="4" marker-end="url(#arrow)"/><g transform="translate(492 173)"><rect width="105" height="86" rx="8" fill="#3a1c1c" stroke="#f87171" stroke-width="2"/><path d="M21 19l63 48M84 19L21 67" stroke="#f87171" stroke-width="4"/><text x="52" y="108" fill="#fca5a5" font-size="10" text-anchor="middle">load ZL = 18 − j24 Ω</text></g><g transform="translate(610 92)"><circle cx="63" cy="63" r="60" fill="#101a28" stroke="#3a4453"/><circle cx="63" cy="63" r="40" fill="none" stroke="#233043"/><path d="M3 63h120M63 3v120" stroke="#3a4453"/><path d="M18 63A45 45 0 00108 63M28 63A35 35 0 0198 63" fill="none" stroke="#64748b"/><circle cx="40" cy="92" r="6" fill="#f87171"/><circle cx="63" cy="63" r="6" fill="#34d399"/><path d="M40 92Q91 96 91 63H63" fill="none" stroke="#f59e0b" stroke-width="2" marker-end="url(#green)"/><text x="63" y="145" fill="#8b98a5" font-size="9.5" text-anchor="middle">normalized Smith chart</text><text x="34" y="107" fill="#fca5a5" font-size="8">ZL</text><text x="69" y="56" fill="#6ee7b7" font-size="8">1+j0</text></g><path d="M82 311H581" stroke="#34d399" stroke-width="2"/><text x="331" y="335" fill="#6ee7b7" font-size="10.5" text-anchor="middle">at f₀: Zin = 50 Ω → Γ = (Zin − Zₛ)/(Zin + Zₛ) = 0</text><path d="M82 365H581" stroke="#f59e0b" stroke-dasharray="6 4"/><text x="331" y="389" fill="#fbbf24" font-size="10" text-anchor="middle">away from f₀, reactance changes and the match degrades</text><text x="380" y="452" fill="#6b7684" font-size="11.5" text-anchor="middle">Matching networks trade bandwidth, loss, component Q, voltage stress, and topology constraints for lower reflection at the target band.</text></svg>

Verification, qualification, and CFS connection. Simulation sweeps process, voltage, temperature, driver impedance, receiver capacitance, stackup tolerance, resistor tolerance, topology, and edge rate. TDR confirms fabricated impedance and finds launches, vias, connectors, and damage. Oscilloscope measurements at the receiver check overshoot, undershoot, settling, eye opening, and timing; probing must not dominate the node. VNA measurements support frequency-domain matching and fixture deembedding. A termination change is accepted only after power, thermal, EMI, startup, unpowered-receiver, and fault behavior are also reviewed. Verification crosses schematic, layout, fabrication, assembly, and laboratory evidence. Automated checks cover connectivity, spacing, drill aspect ratio, annular ring, solder-mask dams, acid traps, copper balance, test access, and assembly courtyard. Field solvers and extracted models check impedance, loss, coupling, return paths, and PDN behavior. Fabrication coupons measure impedance; TDR locates discontinuities; VNA measurements characterize insertion and return loss; oscilloscopes measure eye, jitter, and rail noise. Thermal imaging, current injection, chamber cycling, vibration, X-ray, cross-section, and functional test close physical reliability. A design review preserves raw models, stackups, material declarations, process limits, measurement reference planes, calibration, uncertainty, failure evidence, and revision history so a passing prototype can become a repeatable product. Acceptance criteria distinguish nominal performance from guardband, screening, qualification, and production-control limits. Supplier substitutions trigger review of electrical, thermal, mechanical, chemical, assembly, and reliability assumptions rather than a part-number-only approval. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.