Inner Spacer Formation

# Inner Spacer Formation in Gate-All-Around (GAA) & CFET Architectures

In Gate-All-Around (GAA) nanosheet field-effect transistors and complementary FETs (CFET), inner spacer formation is the critical Front-End-of-Line (FEOL) unit process module that defines the physical gate length ( $$L_g$$ ), provides electrical isolation between the replacement high-k metal gate (HKMG) and the epitaxial source/drain ( $$S/D$$ ) regions, and modulates channel strain. In planar MOSFETs and 3D FinFETs, gate sidewall spacers are formed exclusively on the outer vertical perimeter of the gate electrode. In GAA nanosheet architectures, however, the gate electrode must fully wrap around three or four vertically stacked horizontal silicon channels. This requires forming tiny, self-aligned dielectric isolation plugs—termed inner spacers ( $t_{sp} \approx 5\text{ to }7\,\text{nm}$ )—within the recessed lateral cavities between adjacent nanosheets prior to source/drain selective epitaxy.

Without precisely engineered inner spacers, the subsequent replacement metal gate deposition would fill the inter-sheet cavities directly into the source and drain, causing catastrophic electrical short circuits ( $I_{leak} \to \infty$ ). Conversely, any non-uniformity, over-etching, or chemical degradation during spacer formation alters the effective gate length, induces crystal stacking faults during epitaxial regrowth, or inflates parasitic gate-to-source/drain overlap capacitance ( $C_{ov} = C_{gso} + C_{gdo}$ ), degrading the transistor switching delay ( $\tau = R_{eff} \cdot C_{total}$ ) at leading-edge nodes (3nm, 2nm, and A14).

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## 1. Process Chemistry & Mechanics of Cavity Indentation

The creation of the inner spacer cavity is an atomic-scale subtractive etching challenge. Following dummy polysilicon gate patterning and anisotropic reactive ion etching (RIE) of the source/drain fin recesses, the vertical ends of the alternating silicon nanosheet ( $\text{Si}$ , thickness $t_{ns} \approx 5\text{ nm}$ ) and silicon-germanium sacrificial layers ( $\text{Si}_{1-x}\text{Ge}_x$ , typically $x \approx 0.25\text{ to }0.35$ , thickness $t_{sac} \approx 10\text{ to }12\text{ nm}$ ) are exposed simultaneously.

### 1.1 Chemical Etch Selectivity ( $\text{SiGe}:\text{Si}$ )
The sacrificial $\text{SiGe}$ layers must be selectively etched laterally beneath the dummy gate without attacking or thinning the adjacent crystalline silicon channel sheets. The required etch selectivity $S_{\text{SiGe}/\text{Si}}$ is defined by:

S_{\text{SiGe}/\text{Si}} = \frac{ER_{\text{SiGe}}}{ER_{\text{Si}}} = \frac{r_0 \cdot \exp\left(-\frac{E_{a,\text{SiGe}}}{k_B T}\right)}{r_0 \cdot \exp\left(-\frac{E_{a,\text{Si}}}{k_B T}\right)} \ge 150:1

Where $$ER$$ is the etch rate, $$E_a$$ is the activation energy, $$k_B$$ is the Boltzmann constant, and $$T$$ is temperature. Because the nanosheet thickness is only $5\,\text{nm}$ , any unintended silicon loss greater than $0.5\,\text{nm}$ represents a catastrophic $>10\%$ channel thickness variance, inducing massive threshold voltage shift ( $\Delta V_t \propto \Delta t_{ns}^{-2}$ ) and quantum confinement dispersion.

Two primary dry etching chemistries achieve this extreme selectivity in high-volume manufacturing:
1. Downstream Microwave Plasma Fluorination: Downstream microwave plasma generated from $\text{CF}_4 / \text{O}_2 / \text{N}_2$ or $\text{NF}_3 / \text{NH}_3 / \text{O}_2$ . Atomic fluorine ( $\text{F}^*$ ) reacts exothermically with germanium atoms in the crystal lattice:

\text{Si}_{1-x}\text{Ge}_x + 4\text{F}^* \to (1-x)\text{SiF}_4\uparrow + x\,\text{GeF}_4\uparrow

Germanium acts as a chemical catalyst, drastically lowering the reaction energy barrier relative to pure silicon and yielding selectivities exceeding $$150:1$$ to $$200:1$$ at low substrate temperatures ( $-20^\circ\text{C}\text{ to }40^\circ\text{C}$ ).
2. Thermal Vapor-Phase Halogenation: Gaseous hydrochloric acid ( $\text{HCl}$ ) or chlorine trifluoride ( $\text{ClF}_3$ ) in an ultra-high vacuum chemical vapor chamber. At controlled partial pressures and elevated temperatures ( $500^\circ\text{C}\text{ to }650^\circ\text{C}$ ), $\text{HCl}$ selectively volatilizes $\text{Ge}$ as gaseous germanium chlorides ( $\text{GeCl}_4$ , $\text{GeCl}_2$ ) while crystalline silicon remains thermodynamically stable.

### 1.2 Cavity Indentation Profile Engineering
The lateral indentation depth $L_{indent}$ must be controlled across the wafer with sub-nanometer precision:

L_{indent} = \int_0^{t_{etch}} ER_{\text{SiGe}}(x, y, \tau) \, d\tau \approx ER_{\text{SiGe}} \cdot t_{etch} = 5.5\,\text{nm} \pm 0.3\,\text{nm}

Depending on gas flow dynamics and surface reactant starvation in high-aspect-ratio trenches, the resulting cavity shape can vary:
- Rectangular Profile (Ideal): Uniform lateral etch front, maximizing contact area and mechanical anchoring for the inner spacer plug.
- Crescent / Rounded Profile: Etch rate is highest at the vertical center of the $\text{SiGe}$ layer, creating a concave indentation that increases parasitic capacitance near the channel corners.

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## 2. Quantitative Modeling: Parasitic Capacitance vs. Drive Current

### 2.1 Overlap Capacitance ( $C_{ov}$ ) Mathematical Derivation
The inner spacer serves as the physical dielectric separating the high-k metal gate from the highly doped source/drain epitaxy. For a transistor with $N_{sheets}$ stacked nanosheets, each sheet has an upper and lower inner spacer interface. The total parasitic gate-to-source/drain overlap capacitance $C_{ov}$ is given by:

C_{ov} = C_{gso} + C_{gdo} \approx 2 \cdot N_{sheets} \cdot \left( \frac{\epsilon_0 \kappa_{sp} W_{ns} \cdot H_{cavity}}{t_{sp}} \right)

Where:
- $\epsilon_0 = 8.854 \times 10^{-12}\,\text{F/m}$ is the permittivity of free space.
- $\kappa_{sp}$ is the dielectric constant ( $$k$$ -value) of the inner spacer material.
- $W_{ns}$ is the nanosheet width ( $30\text{ to }40\,\text{nm}$ ).
- $H_{cavity}$ is the cavity height ( $10\text{ to }12\,\text{nm}$ ).
- $t_{sp}$ is the effective spacer thickness ( $5.0\text{ to }6.5\,\text{nm}$ ).

For a standard 3-nanosheet device ( $N_{sheets} = 3$ , $W_{ns} = 35\,\text{nm}$ , $H_{cavity} = 11\,\text{nm}$ , $t_{sp} = 5.5\,\text{nm}$ ):
- Conventional Silicon Nitride ( $\text{Si}_3\text{N}_4$ , $\kappa_{sp} = 7.2$ ):

C_{ov} \approx 2 \cdot 3 \cdot \left( \frac{(8.854 \times 10^{-12}) \cdot 7.2 \cdot (35 \times 10^{-9}) \cdot (11 \times 10^{-9})}{5.5 \times 10^{-9}} \right) \approx 36.2\,\text{aF}

Low-k Silicon Borocarbonitride ( $\text{SiBCN}$ , $\kappa_{sp} = 3.8$ ):

C_{ov} \approx 2 \cdot 3 \cdot \left( \frac{(8.854 \times 10^{-12}) \cdot 3.8 \cdot (35 \times 10^{-9}) \cdot (11 \times 10^{-9})}{5.5 \times 10^{-9}} \right) \approx 19.1\,\text{aF}

Switching from standard $\text{SiN}$ to low-k $\text{SiBCN}$ achieves an immediate $47.2\%$ reduction in parasitic gate capacitance, directly expanding the AC frequency cutoff ( $f_T = g_m / (2\pi C_{total})$ ).

### 2.2 Effective Drive Current & Series Resistance Tradeoff
While thinning the spacer ( $t_{sp} \to 2\,\text{nm}$ ) reduces access length, it drastically increases $C_{ov} \propto 1/t_{sp}$ . Conversely, thickening the spacer ( $t_{sp} > 8\,\text{nm}$ ) reduces capacitance but increases the external source/drain extension series resistance ( $R_{ext}$ ):

R_{ext} = R_{contact} + R_{epi} + R_{extension} \approx R_0 + \frac{\rho_{extension} \cdot t_{sp}}{W_{ns} \cdot t_{ns}}

Where $\rho_{extension}$ is the electrical resistivity of the shallow extension region. The circuit switching delay $\tau$ is governed by the product of total effective resistance and capacitance:

\tau = R_{total} \cdot C_{total} = (R_{ch} + 2 R_{ext}) \cdot (C_{gate} + C_{ov})

Differentiating $\tau$ with respect to $t_{sp}$ reveals a sharp global optimum at $t_{sp} \approx 5.5\text{ to }6.0\,\text{nm}$ , where the reduction in parasitic capacitance balances the increase in series resistance to deliver minimum gate propagation delay.

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## 3. Material Selection: Low-k Dielectric Deposition & Wet/Dry Resistance

The inner spacer material must simultaneously fulfill four demanding physical and chemical requirements:
1. Low Permittivity ( $\kappa < 4.5$ ): To suppress parasitic capacitance.
2. Atomic Layer Conformality: 100% step coverage inside narrow $10\,\text{nm} \times 6\,\text{nm}$ recessed cavities without pinch-off or voiding.
3. Hydrofluoric Acid (HF) Wet Etch Resistance: The spacer must survive the subsequent sacrificial $\text{SiGe}$ channel release etch (which exposes the structure to concentrated or vapor HF solutions).
4. Thermal Stability ( $>850^\circ\text{C}$ ): Surviving the source/drain epitaxial pre-bake ( $750^\circ\text{C}\text{ to }800^\circ\text{C}$ ) and dopant activation anneals ( $>950^\circ\text{C}$ ) without elemental outgassing or morphological blistering.

+----------------------------------------------------------------------------------------------------+
|                               INNER SPACER DIELECTRIC MATERIAL BENCHMARK                           |
+----------------------+--------------------+--------------------+--------------------+--------------+
| PROPERTY             | SILICON NITRIDE    | SILICON CARBONITRIDE| SILICON OXYCARBIDE | SILICON BORON|
|                      | (Si₃N₄ / SiN)      | (SiCN)             | (SiOCN)            | NITRIDE (SiBCN|
+----------------------+--------------------+--------------------+--------------------+--------------+
| Dielectric Const (k) | 7.0 to 7.5         | 5.0 to 5.5         | 4.2 to 4.8         | 3.8 to 4.2   |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Deposition Method    | Thermal / PE-ALD   | Plasma-Enhanced ALD| Plasma-Enhanced ALD| PE-ALD       |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Precursor Chemistries| SiH₂Cl₂ + NH₃      | Dichlorosilane +   | Alkoxysilane +     | BCl₃ + SiH₄ +|
|                      |                    | Alkylamines        | CO₂ / NH₃ plasma   | N₂ plasma    |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Dilute HF Etch Rate  | ~1.5 nm/min        | ~0.4 nm/min        | ~0.8 nm/min        | <0.2 nm/min  |
| (dHF 0.5% at 25°C)   | (Poor selectivity) | (Good resistance)  | (Moderate)         | (Superior)   |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Thermal Stability    | >1050°C            | >950°C             | ~900°C             | >1000°C      |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Leakage Current      | <10⁻⁹ A/cm²        | <10⁻⁸ A/cm²        | <10⁻⁸ A/cm²        | <10⁻⁹ A/cm²  |
| (@ 2 MV/cm)          |                    |                    |                    |              |
+----------------------+--------------------+--------------------+--------------------+--------------+
| Industry Status      | Legacy FinFET      | N5 / N3 GAA        | N3 / N2 GAA        | A14 / CFET   |
+----------------------+--------------------+--------------------+--------------------+--------------+

### 3.1 Why Silicon Borocarbonitride ( $\text{SiBCN}$ ) Dominates Sub-2nm Nodes
$\text{SiBCN}$ has emerged as the premier inner spacer material for 2nm and CFET logic nodes because of the unique synergistic bonding of boron, carbon, and nitrogen within the amorphous silicon network:
- Boron Incorporation: Boron atoms enter the $\text{Si-N}$ lattice, disrupting polarizable bonds and lowering the electronic and ionic polarizability, reducing the bulk dielectric constant to $k \approx 3.8$ .
- Fluorine Etch Resistance: Boron-carbon bonds form a dense, hydrophobic surface network that exhibits negligible chemical reactivity toward fluoride radicals ( $\text{F}^*$ ) and vapor $\text{HF}$ , yielding a wet etch rate $<0.2\,\text{nm/min}$ in dilute hydrofluoric acid. This preserves the inner spacer dimensions throughout the downstream nanosheet release sequence.

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## 4. Defect Modes & Metrology in High-Volume Manufacturing

Because the inner spacer is completely embedded inside the 3D nanosheet lattice beneath the dummy gate, conventional optical metrology cannot inspect it. Manufacturing lines deploy advanced transmission electron microscopy (TEM) and inline atomic force metrology to control five primary defect modes:

+----------------------------------------------------------------------------------------------------+
|                                    INNER SPACER DEFECT MODES & MITIGATIONS                         |
+----------------------+-------------------------------------+---------------------------------------+
| DEFECT MODE          | ROOT CAUSE                          | ELECTRICAL / PHYSICAL CONSEQUENCE     |
+----------------------+-------------------------------------+---------------------------------------+
| Spacer Under-Etch    | Insufficient pull-back dry etch     | Residual dielectric covers nanosheet  |
| (Dielectric residue) | duration or poor loading correction | tips, blocking epitaxial S/D growth   |
|                      |                                     | -> catastrophic open-circuit faults   |
+----------------------+-------------------------------------+---------------------------------------+
| Spacer Over-Etch     | Excessive isotropic pull-back etch; | Spacer is recessed back into cavity   |
| (Spacer punch-thru)  | poor etch selectivity to oxide      | -> High-k metal gate wraps around S/D |
|                      |                                     | -> Massive gate-to-source leakage/short|
+----------------------+-------------------------------------+---------------------------------------+
| Cavity Pinch-Off     | Non-conformal ALD deposition with   | Central sub-nanometer keyhole void    |
| (Keyhole voiding)    | excessive precursor sticking coeff  | forms -> Structural collapse under    |
|                      |                                     | thermal stress; metal gate ingress    |
+----------------------+-------------------------------------+---------------------------------------+
| Silicon Nanosheet    | Poor SiGe:Si etch selectivity       | Non-uniform channel thickness (t_ns)  |
| Gouging / Corner     | (<100:1) during cavity indentation; | -> Severe threshold voltage shift     |
| Rounding             | energetic radical sputtering        | (ΔV_t > 80 mV); drive current deficit |
+----------------------+-------------------------------------+---------------------------------------+
| Stress Relaxation /  | Asymmetric cavity indentation depth | Loss of beneficial longitudinal strain|
| Crystal Dislocation  | between source and drain sides      | in Si channel; misfit dislocations at |
|                      |                                     | epi interface -> degraded mobility    |
+----------------------+-------------------------------------+---------------------------------------+

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## 5. Technology Comparison: Spacer Evolution Across CMOS Generations

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF GATE SIDEWALL SPACERS                          |
+----------------------+---------------------+-----------------------+-------------------------------+
| METRIC               | PLANAR MOSFET (28nm)| 3D FINFET (7nm/5nm)   | GAA NANOSHEET & CFET (2nm/A14)|
+----------------------+---------------------+-----------------------+-------------------------------+
| Spacer Topology      | Single lateral outer| 3D conformally coated | Dual-Spacer System:           |
|                      | vertical sidewall   | vertical fin sidewall | Outer Spacer + Inner Spacer   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Number of Spacers    | 2 per transistor    | 2 per fin             | 2 Outer + 6 to 8 Inner        |
| per Device           | (Source & Drain)    | (Source & Drain)      | Spacers (per 3-sheet stack)   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Spacer Thickness     | 12 nm to 20 nm      | 8 nm to 12 nm         | 5.0 nm to 6.5 nm              |
+----------------------+---------------------+-----------------------+-------------------------------+
| Typical Material     | SiO₂ / Si₃N₄ bilayer| SiOCN / SiCN low-k    | SiBCN ultra-low-k (k ≈ 3.8)   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Cavity Formation Req | None                | None                  | Mandatory isotropic SiGe      |
|                      | (Planar deposition) | (Planar deposition)   | recess etch (Selectivity >150)|
+----------------------+---------------------+-----------------------+-------------------------------+
| S/D Epitaxy Interface| Planar substrate    | 3D fin sidewalls      | Faceted growth anchored       |
|                      |                     |                       | directly between inner spacers|
+----------------------+---------------------+-----------------------+-------------------------------+
| Yield Sensitivity    | Low                 | Moderate              | Extreme (Primary yield limiter|
|                      |                     |                       | in 3nm/2nm GAA development)   |
+----------------------+---------------------+-----------------------+-------------------------------+

Inner Spacer Formation

Take inner spacer formation further