Inner Spacer is a dielectric plug formed in the recessed SiGe sacrificial layer regions adjacent to the channel in nanosheet transistors — electrically isolating the metal gate from the source/drain, reducing gate-to-drain capacitance ($C_{gd}$) and preventing gate leakage to S/D.

Why Inner Spacers Are Needed

• After nanosheet channel release, metal gate surrounds each nanosheet channel.
• Without inner spacers: Metal gate would contact the SiGe S/D epi directly at the ends of the stack.
• Result without inner spacers: Gate-to-drain short + large parasitic $C_{gd}$ → circuit failure.
• Inner spacer creates the insulating boundary between gate and S/D epilayer.

Inner Spacer Formation Process

Step 1 — SiGe Lateral Recess:

• Isotropic selective etch of SiGe layers exposed at nanosheet stack edge.
• Etchant: SC-1 (H2O2 + NH4OH) or dilute H2O2 at 40°C, or HCl gas at 600°C.
• Selectivity SiGe:Si > 100:1 required.
• Recess depth: 5–15nm laterally into stack — defines inner spacer volume.

Step 2 — Inner Spacer Dielectric Deposition:

• ALD dielectric: SiO2, SiN, SiCO, or low-k SiOCN deposited conformally.
• Must fill the lateral SiGe recess completely — ALD ensures conformal fill.
• Thickness: Must equal recess depth (no material outside recess wanted).

Step 3 — Inner Spacer Etch Back:

• Anisotropic etch removes excess inner spacer material from Si nanosheet surfaces and dummy gate top.
• Only material remaining: Lateral recess plugs → inner spacers.
• Critical: Etch back must not damage Si nanosheet surface or outer spacer.

Material Requirements

• Low dielectric constant: Reduces $C_{gd}$ and fringe capacitance.
• SiO2 (k=3.9): Common choice, easy integration.
• SiCO/SiCON (k=3.0–3.5): Lower k → lower Cgd → better AC performance.
• Chemical selectivity: Must survive SiGe channel release and subsequent metal gate fill.

Inner spacers are the critical isolation element unique to nanosheet transistors — their dielectric constant, conformality, and dimensional control directly determine the parasitic capacitance and gate leakage performance that differentiate GAA transistor generations.