An InP/InGaAs heterostructure deliberately places material discontinuities to control carriers. In an InAlAs/InGaAs HEMT, barrier-supplied electrons accumulate in a lower-energy InGaAs channel as a two-dimensional electron gas. In an HBT, a wider-gap InP emitter injects into a narrower-gap InGaAs base. These distinct devices share a need for abrupt, low-defect interfaces with known band alignment.

Read InP/InGaAs heterostructures through a band-offset-confinement lens rather than a bulk-material lens. Bandgaps near 1.34 eV for InP and 0.74 eV for lattice-matched InGaAs cannot predict performance without layer order, strain, doping setback, interface charge, and electrostatics. In a HEMT, the conduction-band discontinuity and remote donor arrangement create and confine the 2DEG. In an HBT, emitter-base band alignment improves injection while the base-collector transition must pass electrons without an unintended barrier. Useful speed and gain follow from the complete heterostructure plus its contacts and geometry.

Lattice matching is the first process decision. In0.53Ga0.47As and In0.52Al0.48As are approximately lattice matched to InP and provide a practical baseline for thick, low-defect stacks. Raising indium above 53% can improve channel transport but makes the InGaAs pseudomorphic, so thickness must stay below a qualified relaxation limit. A 15 nm strained channel may remain coherent where a 50 nm layer of the same composition relaxes. The correct control is reciprocal-space and defect evidence across thickness-composition splits, not nominal gas ratios alone.

Molecular-beam epitaxy, gas-source MBE, chemical-beam epitaxy, and metal-organic vapor-phase epitaxy can all form these stacks. Each establishes different controls for group-III flux, arsenic overpressure, interface switching, carbon or silicon incorporation, and wafer-scale uniformity. Growth temperature trades adatom mobility against interdiffusion and desorption. A 20°C shift can change incorporation and surface morphology even when the thickness monitor is stable, so chamber history and calibrated composition witnesses belong to the run record.

The HEMT separates charge supply from the transport channel. A donor sheet in InAlAs supplies electrons, while an undoped spacer—5 nm in one illustrative design—reduces ionized-impurity scattering before the electrons occupy a 15 nm InGaAs quantum well. A thicker spacer can increase mobility but lower sheet density and transconductance; a thinner spacer does the reverse. One published room-temperature structure reported about 11230 cm²/V·s mobility at 2.3 × 10^12 cm^-2 sheet density. That pair of values is meaningful only with composition, temperature, spacer, buffer, and measurement method.

The gate controls the 2DEG through an InAlAs barrier and recess geometry. An illustrative barrier may be 15 nm thick before recess, with a final gate-to-channel separation controlled within 2 nm. Over-etching raises gate leakage and process sensitivity; under-etching reduces gate control and shifts threshold. A 100 nm T-gate can reduce gate resistance, but the effective electrostatic length also depends on recess profile and lateral access resistance. Gate length alone is therefore not a complete speed metric.

Surface chemistry can erase an excellent buried channel. InGaAs and InAlAs form complex native oxides, and recess or mesa etches can leave arsenic-rich, oxidized, or damaged surfaces. XPS can compare surface composition before and after clean/passivation splits. AFM can map morphology over a 5 µm field and enforce an illustrative 0.4 nm roughness limit. Passivation must reduce dispersion and leakage without adding unacceptable parasitic capacitance. A 20 nm dielectric may stabilize the surface while changing field distribution and access capacitance, so DC, pulsed, and RF evidence must travel together.

Ohmic contacts should be evaluated as interfaces, not just metal recipes. Non-alloyed contacts to highly doped InGaAs can avoid aggressive thermal reactions, but contact resistivity still depends on cap doping, recess, surface preparation, and metal. Transmission-line or Kelvin structures separate contact resistance from sheet resistance; four-point probe maps suitable blanket layers. If total source resistance rises 10%, transconductance and noise can degrade even when Hall effect mobility is unchanged. Contact anneal and passivation order must be included in reliability splits.

The HBT uses the same materials for a different band-engineering task. A wide-gap InP emitter suppresses reverse hole injection into a p-InGaAs base, supporting high injection efficiency with a heavily doped, thin base. An illustrative base may be 40 nm thick, but its electrical transit width depends on dopant placement and junction depletion. A double-heterojunction device also uses InP on the collector side for voltage capability. The InGaAs-to-InP base-collector discontinuity can impede electrons, so composition grading or a superlattice transition is used to smooth transport.

Collector design balances transit, avalanche, and capacitance. A thinner or more highly doped collector can reduce transit delay while increasing electric field and collector-base capacitance. One device option may target operation near 2 V, while another reserves 5 V for breakdown margin at lower peak speed. The appropriate metric set includes common-emitter breakdown, collector-base breakdown, output conductance, gain, and current-density-dependent transit response. Quoting one fT value without voltage and geometry is incomplete.

Composition profiles must be measured with finite-resolution awareness. SIMS can profile silicon, carbon, and alloy-related signals, but sputter mixing and matrix-dependent yield broaden abrupt III-V interfaces. A measured 8 nm transition may include 3 nm of instrumental broadening rather than 8 nm of physical grading. High-resolution X-ray diffraction constrains average composition, thickness, strain, and interface periodicity through a stack model. ellipsometry adds wafer-scale thickness sensitivity where optical constants and layer correlations are controlled. Cross-sectional microscopy anchors individual interfaces and relaxation defects.

Hall effect measurements give sheet density and mobility for the epitaxial transport system. They do not directly include gate recess damage, source resistance, or short-channel electrostatics. A room-temperature mobility of 10000 cm²/V·s with a 2.5 × 10^12 cm^-2 sheet density can coexist with poor transistor transconductance if contacts or access regions dominate. Temperature-dependent Hall effect helps separate scattering mechanisms, while gated Hall measurements can distinguish free carriers from trapped charge in MOS-like InGaAs channels.

An InGaAs MOSFET is not merely a HEMT with an oxide. A MOS structure places the gate dielectric directly in the electrostatic control path, making interface traps and border traps central. Fast traps can distort capacitance-based charge estimates, threshold, subthreshold slope, and mobility extraction. A NIST-reported gated-Hall study found 1800 cm²/V·s mobility near 1 × 10^12 cm^-2 inversion density while demonstrating that capacitance-derived carrier density could be overestimated. Gate-stack qualification must therefore include trap-sensitive frequency, temperature, and time-domain measurements.

For RF characterization, Keysight network analyzers can measure S-parameters over a declared bias and frequency range. Open, short, and through structures support pad and interconnect de-embedding. A historical 1 µm MOCVD HEMT demonstrated 60000 MHz fT and 120000 MHz fmax, while submicron structures in the same study reached higher values; these are examples of process and geometry dependence, not contemporary product targets. Keithley instruments can acquire transfer, output, gate-leakage, breakdown, and pulsed-stress data at the same coordinates.

Thermal and bias reliability must distinguish mechanisms. InP has lower thermal conductivity than silicon, and narrow mesas concentrate heat. Self-heating changes mobility, current gain, contact resistance, and trap occupancy. A qualification matrix might compare 25°C, 85°C, and 125°C operation; 1 V, 2 V, and 3 V stress; and 1 ms versus 100 ms pulses. Current collapse after a long quiescent bias suggests trapping, while permanent leakage growth suggests damage. DLTS can identify deep levels on appropriate structures, but device-relevant trapping also needs pulsed electrical evidence.

III-V-on-silicon integration changes defect and thermal boundaries. Direct growth must manage lattice mismatch and threading defects. Bonding transfers qualified material but adds alignment and thermal-interface constraints; selective growth adds loading and facet variation. Choose by active-area density, thermal path, interconnect pitch, and defect tolerance rather than a generic integration label.

Select HEMT, HBT, MOSFET, or optoelectronic device requirements
  -> Choose lattice-matched or pseudomorphic InP-based stack
  -> Grow buffer, barriers, channel or base, cap, and contact layers
  -> Verify composition, strain, thickness, roughness, and depth profiles
  -> Pattern mesa and isolation with surface-damage controls
  -> Form HBT emitter/base alignment or HEMT/MOS gate recess
  -> Clean, passivate, and form low-resistance contacts
  -> Map Hall mobility, sheet density, sheet resistance, and contact resistance
  -> Acquire DC transfer, Gummel, leakage, gain, and breakdown distributions
  -> De-embed RF structures and extract fT, fmax, capacitance, and resistance
  -> Run pulsed-bias, temperature, trapping, and aging experiments
  -> Correlate failures to interfaces, profiles, recess, contacts, and heat
  -> Evaluate native InP or heterogeneous silicon integration path
  -> Release only when material, device, and reliability windows overlap

Release requires proof of confinement and transport at device scale. A credible InP/InGaAs process links calibrated epitaxy to interface chemistry, band alignment, carrier density, mobility, recess geometry, contacts, passivation, DC behavior, RF extraction, and reliability. When gain or speed shifts, the investigation should first decide whether the cause is a heterostructure profile, trapped charge, access resistance, capacitance, or self-heating. That band-offset-confinement lens prevents attractive bulk material properties from being mistaken for a manufacturable high-frequency device.