Interconnect Electromigration (EM) and Void Formation

Interconnect Electromigration (EM) and Void Formation is the reliability failure mechanism where DC current flowing through metal wires physically transports copper atoms in the direction of electron flow — gradually creating voids at current-divergence points (cathode) and hillocks/extrusions at anode sites, eventually severing or shorting circuit connections, with failure time following log-normal statistics and strongly depending on current density, temperature, and copper microstructure.

Electromigration Physics

- Electric current exerts "electron wind force" on metal ions: F = Z*eρj
- Z* = effective charge number (includes direct field force + electron wind)
- ρ = metal resistivity, j = current density
- Copper: Z* ≈ -12 → atoms move in direction of electron flow (toward anode).
- Diffusion paths: Grain boundaries >> surface >> interfaces >> bulk → grain boundary engineering critical.

Black's Equation (EM Lifetime)

- Mean time to failure (MTTF) = A × j^(-n) × exp(Ea/kT)
- A: Geometry/material constant
- j: Current density (mA/µm²)
- n: Current density exponent (typically 1–2 for steady DC)
- Ea: Activation energy (Cu grain boundary ≈ 0.9 eV; Cu/SiN cap interface ≈ 0.7 eV)
- T: Absolute temperature
- Strong T and j sensitivity: Doubling j → 4× shorter lifetime (n=2); +10°C → 1.8× shorter.

Void and Hillock Formation

- Cathode void: Atoms leave cathode → vacancy accumulates → void nucleates → grows → open circuit failure.
- Anode hillock: Atom accumulation at anode → copper extrusion → shorting to adjacent wire → short circuit failure.
- Void location: Forms at current crowding points: vias (current enters/exits wire), corners, narrow segments.

EM Testing and Acceleration

- JEDEC standard EM test: Stress at high current density (5–20× nominal) and high temperature (200–300°C).
- Extrapolate to operating conditions using Black's equation.
- Typical test: 300 hours at 300°C, 10 mA/µm² → extrapolate to 10-year at 105°C, 1 mA/µm².
- Log-normal distribution: Plot ln(time) → normal distribution → extract mean and sigma.

EM Design Rules

- Maximum current density limits: TSMC N5 metal 1: ~2.5 mA/µm width for DC.
- Width de-rating: Wide wires have better EM reliability → design tools enforce minimum width at given current.
- Via redundancy: Multiple vias at high-current nodes → distributes current → reduces j at each via.
- Thermal de-rating: Higher operating temperature → apply current density de-rating factor.
- AC vs DC: Bidirectional AC current → average EM effect smaller → separate AC and DC EM limits.

Copper Microstructure and EM Resistance

- Grain size: Larger grains → fewer grain boundary diffusion paths → better EM resistance.
- Texture: (111)-oriented copper grains → lower surface diffusion → 2–3× better EM lifetime.
- Bamboo structure: Grain boundaries perpendicular to current flow (not parallel) → blocks EM diffusion path → in narrow wires (< 200nm) naturally forms bamboo → excellent EM resistance.

Capping Layer Role

- Cu/SiN interface: Fast diffusion path → use CoWP (cobalt tungsten phosphide) or Mn-based self-forming barrier cap → reduces interface diffusion → 10–100× EM improvement.
- TSMC N7/N5: CoWP selective cap on Cu → enables higher current density at same reliability.

EM in Advanced Nodes

- Narrower wires: Current density increases for same current → worse EM.
- Ruthenium (Ru) wiring: Considered for M0/M1 → better EM resistance than Cu at narrow dimensions.
- Resistance to EM: Ru-Cu integration or full Ru → active research at sub-7nm.

Interconnect electromigration is the reliability tax on high-performance chip design — because current density increases as wires scale narrower while EM lifetime falls exponentially with current density, meeting 10-year automotive reliability requirements for a 3nm chip operating at 1A total current requires careful EM-aware routing with wide wires at current-critical nodes, redundant vias, and operating temperature management, making EM analysis a mandatory signoff step that directly constrains the maximum safe operating current of every metal wire in the 10km of interconnect packed into a modern chip die.