Home Knowledge Base HPC Interconnect Topologies

HPC Interconnect Topologies are the physical and logical network structures that connect compute nodes in a supercomputer or data center cluster — where the choice of topology (fat tree, dragonfly, torus, mesh) determines the bisection bandwidth, diameter, cost, and scalability of the system, directly impacting the performance of communication-intensive parallel applications by 2-10x compared to a mismatched topology.

Why Topology Matters

Parallel applications communicate through the interconnect — MPI collectives, distributed-memory data exchange, gradient synchronization in distributed training. The interconnect's bandwidth, latency, and congestion characteristics under real traffic patterns determine whether computation or communication is the bottleneck. A topology optimized for the workload's communication pattern can halve runtime.

Key Topologies

Key Metrics

MetricDefinitionImpact
Bisection BandwidthTotal bandwidth across a minimum cut dividing the network in halfDetermines max all-to-all throughput
DiameterMaximum hops between any two nodesDetermines worst-case latency
Node Degree (Radix)Number of links per node/switchDetermines hardware cost per node
Path DiversityNumber of alternative paths between node pairsDetermines congestion resilience

Adaptive and Minimal Routing

Modern interconnects use adaptive routing — dynamically selecting among multiple shortest-path alternatives based on real-time congestion information from switch buffers. Non-minimal (Valiant) routing sends packets through a random intermediate node, provably balancing load at the cost of doubling average hop count.

HPC Interconnect Topologies are the circulatory system of parallel computing — determining how fast data flows between the processors that form the parallel machine, and representing one of the most impactful architectural decisions in system design.

interconnect topology hpcnetwork topology clusterfat tree dragonflytorus mesh topologyhigh radix switch

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