Ion implantation is the universal doping method in semiconductor manufacturing — accelerating ionized dopant atoms (B⁺, P⁺, As⁺, BF₂⁺) to energies from 0.2 keV to several MeV and driving them into the silicon lattice with sub-percent dose uniformity across a 300 mm wafer. Every transistor in a modern chip — source/drain junctions, threshold-voltage adjust, well formation, halo/pocket implants, lightly-doped drain extensions — is defined by one or more implant steps. A leading-edge logic flow contains 30–50 separate implant operations; a DRAM flow, 20–30.
How it works — the beam line. A gas source (BF₃, PH₃, AsH₃) feeds an ion source (Freeman, Bernas, or inductively-coupled plasma) where a hot filament or RF plasma ionizes the precursor. A mass-analyzing magnet bends the extracted beam through a ~90° arc, selecting the desired isotope/charge-state by its mass-to-charge ratio $m/q$. The filtered beam is then accelerated (or decelerated for ultra-low-energy implants) to the target energy and electrostatically or magnetically scanned across the wafer. Dose is controlled by integrating beam current × time over the wafer area:
$$\text{Dose (atoms/cm}^2) = \frac{I \cdot t}{q \cdot A}$$
where $I$ is beam current (µA to tens of mA), $t$ is exposure time, $q$ is ion charge, and $A$ is the implanted area.
Depth profile — the LSS theory. An implanted ion loses energy through nuclear collisions (elastic scattering off Si atoms, dominant at low energy) and electronic stopping (inelastic drag from the electron cloud, dominant at high energy). The resulting depth distribution is approximately Gaussian, characterized by:
$$n(x) = \frac{\Phi}{\sqrt{2\pi}\,\Delta R_p} \exp\!\Bigl(-\frac{(x - R_p)^2}{2\,\Delta R_p^2}\Bigr)$$
where $R_p$ is the projected range (mean depth), $\Delta R_p$ is the straggle (standard deviation), and $\Phi$ is the dose. Real profiles deviate from Gaussian — they develop skewness (third moment) and kurtosis (fourth moment) described by Pearson-IV or dual-Pearson models, especially for light ions like boron in silicon.
| Dopant | Type | Mass (amu) | Typical energy | $R_p$ in Si | Use case |
|---|---|---|---|---|---|
| B⁺ | p | 11 | 0.5–80 keV | 2–300 nm | Wells, Vth adjust, S/D (deep) |
| BF₂⁺ | p | 49 | 2–30 keV | 5–40 nm | Ultra-shallow p+ S/D (effective B energy = E×11/49) |
| P⁺ | n | 31 | 10–500 keV | 15–600 nm | n-wells, NLDD, deep retrograde |
| As⁺ | n | 75 | 5–200 keV | 5–120 nm | n+ S/D (heavy → shallow, amorphizing) |
| In⁺ | p | 115 | 50–300 keV | 20–80 nm | Halo/pocket (retrograde p) |
| Ge⁺ | — | 74 | 5–30 keV | 5–30 nm | Pre-amorphization implant (PAI) |
| C⁺ | — | 12 | 2–10 keV | 5–30 nm | TED suppression co-implant |
Channeling — the crystal matters. Silicon is a diamond-cubic crystal with open "channels" along ⟨110⟩ and ⟨100⟩ directions. If the beam enters aligned to a channel, ions penetrate far deeper than the amorphous stopping model predicts (channeling tail). Mitigation: tilt the wafer 7° and twist 22° off-axis, or pre-amorphize the surface with Ge or Si to destroy the crystal order before the dopant implant.
Damage and amorphization. Each implanted ion displaces ~1000 Si atoms from lattice sites through collision cascades. At low doses, isolated point defects (vacancies + interstitials) form. Above a critical dose (~10¹⁴ cm⁻² for heavy ions like As at room temperature), damage regions overlap and the surface layer becomes fully amorphous. The amorphous/crystalline (a/c) interface depth depends on ion mass, energy, dose, and wafer temperature.
Annealing — repairing damage and activating dopants. Implanted atoms sit on interstitial or random sites and are electrically inactive until thermal annealing places them on substitutional lattice sites. The trade-off: higher temperature activates more dopant but also drives diffusion, broadening the profile. Modern solutions:
- Rapid thermal anneal (RTA): 1000–1100°C for 1–10 s (spike anneal). Standard for most implants.
- Millisecond anneal (MSA): flash lamp or laser, 1100–1300°C for 0.1–3 ms. High activation with minimal diffusion — critical for ultra-shallow junctions at ≤7 nm nodes.
- Solid-phase epitaxial regrowth (SPER): 500–650°C for minutes. The amorphous layer recrystallizes from the a/c interface upward at ~1 nm/s, incorporating dopants at >99% activation with near-zero diffusion. Used for ultra-shallow extensions in GAA flows.
Transient enhanced diffusion (TED). Implant-generated interstitials are mobile even at moderate temperatures and "kick" substitutional dopant atoms into interstitial sites where they diffuse rapidly. Boron is especially susceptible — TED can push a junction 20–50 nm deeper than the as-implanted profile. Mitigation: carbon co-implant (traps interstitials), low-temperature SPER anneal, or amorphization + MSA to annihilate defects before they migrate.
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<text x="380" y="435" fill="#d4d4d0" font-size="11" text-anchor="middle">Modern GAA/FinFET flows: 30–50 implant steps per device layer × multiple anneal strategies</text>
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Implant for GAA nanosheet transistors. At the 3 nm node and below, implant requirements tighten further: ultra-shallow source/drain extensions (junction depth $x_j$ < 5 nm), conformal doping of stacked nanosheets (plasma doping or angled implants at multiple rotations), and atomic-precision threshold-voltage tuning through work-function dipole implants at the HKMG interface. The implant + anneal budget is the primary constraint on junction abruptness — which directly determines short-channel control (DIBL, subthreshold swing) in the CFS Transistor Simulator at /transistor.
Equipment landscape. High-current implanters (Axcelis Purion H, Applied Varian VIISta) handle the high-dose S/D implants (10¹⁵–10¹⁶ cm⁻²) at beam currents up to 60 mA. Medium-current tools do well and Vth adjust (10¹²–10¹⁴ cm⁻²). High-energy implanters (1–4 MeV) form deep retrograde wells. Plasma-doping (PLAD) tools provide conformal low-energy doping for 3D structures without line-of-sight limitations — increasingly important for GAA and CFET architectures.
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