IR Drop Signoff is the physical verification step that confirms the power delivery network (PDN) maintains sufficient voltage at every logic cell and memory across the die under all operating conditions — ensuring that resistive voltage drop (I × R) along the power grid from the package to the most current-hungry cells never exceeds the design budget. A 50–100 mV IR drop violation at critical cells can slow timing by 5–15%, causing functional failures in silicon even when all timing checks pass at nominal voltage.

IR Drop Fundamentals

• Ohm's Law on chip: V_drop = I_cell × R_grid_path.
• R_grid_path = sum of resistances from VDD pad through metal layers to cell power pin.
• Metal resistance increases at each node (narrower wires, thinner metals) → IR drop challenge worsens.
• IR drop reduces effective VDD at cell → transistors slower → setup timing violations.

Static vs. Dynamic IR Drop

Static IR Drop

• Represents steady-state condition: cells switching at constant average activity.
• Input: Power grid netlist (metal layer resistances) + current map (average power per cell from vectorless or vector-based analysis).
• Solve: KCL (Kirchhoff's Current Law) at every node in the power grid → V at each node.
• Result: Color-coded IR drop map → identify hotspots.
• Target: Static IR drop < 3–5% of VDD (e.g., < 35 mV at VDD = 0.7 V).

Dynamic IR Drop

• Represents peak voltage droop during simultaneous switching events.
• Input: Simulation vectors (functional patterns or synthetic switching vectors) + grid parasitics (R + C).
• Transient current spikes: Clock tree switching, cache read, bus activity → large simultaneous current → instantaneous droop.
• On-chip decap (decoupling capacitor): Absorbs transient current → reduces peak droop.
• Target: Dynamic IR peak < 10% of VDD (worst-case droop including decap).

IR Drop Analysis Tools

PDN Modeling

• Extract power grid as R-C network from P&R database (DEF + tech file).
• Include: TSV resistance (3D ICs), bump inductance, package PCB resistance.
• Decoupling capacitors: Filler cells with caps, deliberate decap insertion, IO ring decap.
• Mutual inductance: Power and ground loops → L × di/dt → simultaneous switching noise (SSN).

IR Drop Fixing

• Widen power straps: Reduce resistance → lower IR. Cost: More metal area.
• Add power straps: More parallel paths → reduce R. Cost: Routing congestion.
• Insert decap cells: Reduce dynamic droop. Cost: Area.
• Reduce current density: Restructure logic, add pipeline stages, reduce clock frequency.
• Move power pads: Closer to hotspot cells → shorter grid path → lower R.
• BPR/BSPDN: Backside power rails → lower resistance, more width available.

IR Drop-Aware Timing Signoff

• Standard STA: Assumes all cells operate at nominal VDD.
• IR drop-aware STA: Apply per-cell VDD derating based on IR drop map → cells in hotspot run at 0.65 V instead of 0.7 V → timing re-computed with lower VDD → catch violations that standard STA misses.
• Combined IR + STA signoff: Required for all advanced node tapeouts.

IR drop signoff is the power integrity guardrail that ensures every transistor on the chip receives the voltage it was designed for — as current demands grow with higher performance and metal resistivity increases with narrower wires at each new node, IR drop analysis has evolved from a post-layout check to a first-class physical design constraint that shapes floorplan, routing, and cell placement from the earliest stages of physical implementation.