Isotropic etching is the non-directional chemical removal of material at identical rates in all spatial orientations ($R_{\text{lateral}} = R_{\text{vertical}}$, degree of anisotropy $A_f = 0.00$), driven purely by spontaneous, thermally activated radical reactions ($F$, $Cl$, $OH$, $H$) without directional ion-bombardment assistance. In advanced semiconductor manufacturing across 3nm/2nm Gate-All-Around (GAA) NanoSheet architectures, 3D NAND sacrificial layer stripping, and MEMS release processes on tools from Lam Research (Equinox, Selective Etch), Tokyo Electron (Certas LEAG, INDY), and Applied Materials (Producer Selectra), isotropic etching enables ultra-high chemical selectivity ($SiGe:Si > 150:1$, $Si_3N_4:SiO_2 > 100:1$) to recess sub-5nm sacrificial films with zero ion-induced lattice damage ($\Delta V_{\text{th}} = 0\text{ mV}$) and sub-angstrom atomic layer etching (ALE) precision.

Remote Plasma Generation (RPS Microwave, NF3/O2/N2) → Electrostatic/Magnetic Ion Filter (Ion Flux = 0) → Thermal Neutral Radical Beam (F*, Cl*, OH*) → Substrate Surface Transport → Spontaneous Chemical Surface Adsorption → Volatile By-Product Desorption (SiF4 ↑, GeF4 ↑) → Uniform 360° Isotropic Cavity Recess → High Selectivity Stop (SiGe:Si > 150:1) → Damage-Free Atomic Channel Surface

The fundamental chemical mechanism of isotropic etching is driven by spontaneous, non-directional surface reactions unassisted by momentum transfer. Unlike anisotropic reactive ion etching (RIE), which requires perpendicular ion bombardment to break chemical bonds and sputter surface passivants, isotropic etching relies exclusively on the thermal energy of reactive neutral radicals ($F$, $Cl$, $H$, $OH$, $O$) reacting spontaneously with target substrate atoms. The reaction rate obeys standard Arrhenius surface kinetics $R_{\text{iso}} = k_0 [C_{\text{radical}}]^n \exp(-E_a / k_B T)$, where $E_a$ is the chemical activation energy for volatile product formation. Because gas-phase radicals possess an isotropic velocity distribution with zero directional bias, chemical attack occurs at identical rates along all crystallographic planes ($R_x = R_y = R_z$), yielding a degree of anisotropy $A_f = 1 - (R_{\text{lateral}} / R_{\text{vertical}}) = 0.00$ and producing a characteristic $1:1$ undercut beneath mask edges where lateral undercut distance $d_{\text{undercut}}$ equals vertical etch depth $h_{\text{etch}}$.

Remote Plasma Sources (RPS) eliminate charged particle bombardment to achieve pure radical chemical etching. To prevent energetic ions ($10\text{ eV}$ to $1000\text{ eV}$) and vacuum ultraviolet (VUV) photons from reaching the wafer and causing directional sputtering or electrostatic gate oxide damage, advanced isotropic etch systems utilize a remote plasma source mounted upstream of the main process chamber. A high-power microwave ($2.45\text{ GHz}$) or inductively coupled RF ($13.56\text{ MHz}$) discharge dissociates precursor gases ($NF_3$, $CF_4$, $O_2$, $H_2$, $NH_3$) into free radicals and ions inside a quartz or sapphire applicator tube. The gas mixture then passes through a grounded electrostatic grid filter and a tortuous showerhead flow path, recombining $99.999\%$ of ions and electrons ($n_i / n_0 < 10^{-7}$) while delivering a pure, thermalized beam of neutral radicals ($T_{\text{gas}} \approx 300\text{ K}$ to $450\text{ K}$) to the wafer surface.

In Gate-All-Around (GAA) NanoSheet Transistor fabrication, isotropic $SiGe$ selective recess etching defines the inner spacer and channel dimensions. As CMOS logic scaled beyond the $3\text{ nm}$ node at TSMC, Samsung, and Intel, 3D FinFETs were succeeded by GAA NanoSheet architectures (Multi-Bridge-Channel FETs, MBCFETs), which comprise vertical stacks of 3 to 4 single-crystal silicon channels ($t_{\text{sheet}} = 5\text{ nm}$, width $W_{\text{sheet}} = 30\text{ nm}$ to $50\text{ nm}$) separated by sacrificial silicon-germanium layers ($Si_{0.70}Ge_{0.30}$, $t = 10\text{ nm}$). Following vertical fin patterning, an ultra-selective dry isotropic etch must selectively recess the $SiGe$ sacrificial layers laterally by $L_{\text{recess}} = 15\text{ nm}$ to create cavities for dielectric inner spacers ($SiN/SiBCN$) without thinning or roughening the adjacent $5\text{ nm}$ silicon nanosheets. Using vapor-phase $CF_4/O_2/N_2$ or $NF_3/H_2$ remote plasma chemistry, fabs achieve $Si_{0.70}Ge_{0.30}:Si$ chemical selectivity $> 150:1$, limiting silicon channel thickness loss to $< 0.2\text{ nm}$ ($< 4\%$ channel erosion) and preserving high electron mobility.

Thermal Isotropic Atomic Layer Etching (ALE) achieves self-limiting sub-angstrom recession through sequential surface modification and removal cycles. While conventional continuous isotropic etching can suffer from radical transport non-uniformity across complex 3D nanostructures, thermal isotropic ALE separates the chemical reaction into two self-limiting sequential half-cycles. In Step A (surface modification), a fluorinating precursor ($HF$, $NF_3$, or $XeF_2$) reacts with the surface to form a stable, thin modified surface layer (such as $AlF_3$ on $Al_2O_3$ or a fluorinated metal layer) at $T = 200^\circ\text{C}$ to $300^\circ\text{C}$ until all surface active sites are saturated ($S_a \to 0$). In Step B (ligand exchange / volatile desorption), a metal complex precursor (such as trimethylaluminum $Al(CH_3)_3$ or $VO(acac)_2$) is introduced, undergoing ligand exchange reactions that convert the modified layer into volatile organometallic complexes that desorb completely, leaving the underlying unreacted substrate untouched. Thermal isotropic ALE yields precise removal of $0.5\text{ \AA}$ to $1.2\text{ \AA}$ per cycle with $100\%$ self-limitation and zero ion-induced surface damage.

Isotropic wet and dry etching of silicon nitride ($Si_3N_4$) sacrificial layers enables 3D NAND wordline gate replacement. In 3D NAND flash memory manufacturing (128-tier to 300-tier stacks), alternating layers of silicon oxide ($SiO_2$, $t = 30\text{ nm}$) and sacrificial silicon nitride ($Si_3N_4$, $t = 30\text{ nm}$) are deposited in a blanket stack. After memory holes and slit trenches (block divides) are etched vertically, an isotropic selective etch is performed through the narrow slit trench ($W_{\text{slit}} = 150\text{ nm}$, depth $D = 8\ \mu\text{m}$) to remove all $Si_3N_4$ layers completely across lateral distances of $> 1.2\ \mu\text{m}$, creating horizontal cavities that are subsequently backfilled with high-k barrier dielectrics ($Al_2O_3$, $HfO_2$) and tungsten ($W$) or molybdenum ($Mo$) wordline gate metal. Fabs utilize hot phosphoric acid ($H_3PO_4$ at $155^\circ\text{C}$ to $165^\circ\text{C}$) or dry remote plasma $NF_3/O_2/H_2$ chemistries achieving $Si_3N_4:SiO_2$ selectivity $> 100:1$, preventing oxide collapse while stripping up to 300 nitride layers simultaneously.

Metrology and selectivity qualification for isotropic processes at TSMC, Intel, Samsung, SK hynix, Micron, and IBM combine inline spectroscopic ellipsometry, HR-TEM, and atomic force microscopy (AFM). Qualifying isotropic recess etches requires verifying sub-nanometer CD loss, sidewall roughness, and interface cleanliness modeled in Synopsys Sentaurus and Coventor SEMulator3D. Fabs deploy KLA SpectraShape scatterometry and high-resolution transmission electron microscopy (HR-TEM) to inspect $SiGe$ inner spacer cavity depth ($15\text{ nm} \pm 0.4\text{ nm}$) and channel surface roughness ($R_a < 0.15\text{ nm}$). Electrical yield qualification tracks transistor threshold voltage shift ($\Delta V_{\text{th}} < 2\text{ mV}$) and subthreshold swing ($SS < 65\text{ mV/dec}$), confirming that zero ion bombardment from remote plasma processing preserves pristine oxide-semiconductor interface state densities ($D_{\text{it}} < 10^{10}\text{ eV}^{-1}\text{cm}^{-2}$).

Read Isotropic Etch through a thermal-chemical selectivity lens rather than an uncontrolled undercut lens. In advanced 3D semiconductor manufacturing, isotropic etching is not a primitive or unwanted non-directional process; it is an exquisitely tuned, zero-damage surgical tool that enables GAA NanoSheet channel release, 3D NAND gate replacement, and atomic layer precision. Every critical performance metric in isotropic processing — from Arrhenius radical kinetics and remote plasma ion filtering to $SiGe:Si$ selectivity ratios and self-limiting thermal ALE cycles — reflects the mastery of pure chemical thermodynamics over physical momentum transfer. Master these selective chemical reaction mechanisms, and your process integration models will accurately capture channel profile preservation, inner spacer formation, and electrical drive current yields across 2nm and 3D chip architectures.

Pure Spontaneous Chemical Etch Kinetics and Arrhenius Activation

Spontaneous isotropic chemical etching occurs when reactive neutral radicals adsorb on a surface and undergo exothermic chemical reactions without kinetic energy input from ions.

Fluorine radicals react with silicon via a low activation energy barrier ($E_a = 0.108\text{ eV}$), producing volatile $SiF_4$ gas. Because no ion momentum is involved, the reaction rates across (100), (110), and (111) crystal planes are identical.

The rate of spontaneous chemical etching $R_{\text{iso}}$ of silicon by atomic fluorine is expressed mathematically as: $$R_{\text{iso}}(T) = \frac{1}{\rho_{\text{Si}}} k_0 \cdot \Gamma_F \cdot \exp\left(-\frac{E_a}{k_B T}\right)$$ where $\rho_{\text{Si}} = 5.0 \times 10^{22}\text{ atoms/cm}^3$, $\Gamma_F = \frac{1}{4} n_F \bar{v}_F$ is fluorine radical flux ($n_F = 10^{15}\text{ cm}^{-3}$, $\bar{v}_F = 578\text{ m/s}$ at $300\text{ K} \implies \Gamma_F = 1.45 \times 10^{19}\text{ radicals/(cm}^2\cdot\text{s)}$), pre-exponential constant $k_0 = 2.86 \times 10^{-13}\text{ cm}^3/\text{radical}$, and $E_a = 0.108\text{ eV}$ ($1253\text{ K}$). Evaluating at $T = 300\text{ K}$: $$\exp\left(-\frac{0.108\text{ eV}}{0.02585\text{ eV}}\right) = \exp(-4.178) = 0.01532$$ Yielding a spontaneous vertical and lateral silicon etch rate of $R_{\text{iso}} = 1.22\ \mu\text{m/min}$ with zero ion assistance.

Degree of Anisotropy and Undercut Profile Physics

The degree of anisotropy $A_f$ quantifies the directional selectivity of an etch process, where $A_f = 0$ represents perfectly spherical isotropic undercut.

In isotropic etching ($A_f = 0.00$), lateral undercut $d_l$ equals vertical depth $d_v$. Total CD expansion is twice the undercut distance ($\Delta CD = 2 \cdot d_l$), defining the critical dimension bias.

The mathematical profile of an isotropic etch opening of width $W$ beneath a mask edge is modeled by solving the eikonal equation for front propagation $\left|\nabla T_{\text{front}}\right| = 1 / R_{\text{iso}}$: $$r(x, z, t) = \sqrt{(x - x_{\text{mask}})^2 + z^2} = R_{\text{iso}} \cdot t_{\text{etch}}$$ For a straight mask edge at $x = 0$, the profile under the mask is a quarter-circle of radius $R_{\text{iso}} t_{\text{etch}}$. The total Critical Dimension (CD) of the etched trench at the top interface is: $$CD_{\text{final}} = W_{\text{mask}} + 2 \cdot R_{\text{iso}} t_{\text{etch}} = W_{\text{mask}} + 2 h_{\text{etch}}$$ This $2:1$ CD expansion ratio limits conventional isotropic etching to blanket films, release steps, and sacrificial recesses where lateral clearance is desired.

Downstream Remote Plasma Sources (RPS) and Radical Filtering

Remote plasma source (RPS) technology separates plasma generation from the wafer chamber, delivering a charged-particle-free radical stream to the substrate.

An upstream 2.45 GHz microwave source dissociates $NF_3/O_2$. Charged particles recombine across a grounded filter grid ($n_i / n_0 < 10^{-7}$), delivering a pure thermal radical beam to the wafer.

The ion decay along the transport tube of length $L$ and diameter $d_{\text{tube}}$ between the RPS applicator and showerhead is governed by ambipolar wall recombination kinetics: $$n_i(L) = n_{i,0} \exp\left( -\frac{2 J_{\text{wall}}}{e v_{B,i} r_{\text{tube}}} L \right) = n_{i,0} \exp\left( -\frac{D_a \chi_{01}^2}{r_{\text{tube}}^2 \bar{v}} L \right)$$ where $D_a \approx 4.5 \times 10^3\text{ cm}^2/\text{s}$ is ambipolar diffusion coefficient at $1\text{ Torr}$, $r_{\text{tube}} = 2.5\text{ cm}$, and $\chi_{01} = 2.405$ is the first zero of the $J_0$ Bessel function. For a transport length $L = 45\text{ cm}$, the exponential attenuation factor is $\exp(-18.4) = 1.02 \times 10^{-8}$, reducing ion density from $n_{i,0} = 5 \times 10^{11}\text{ cm}^{-3}$ inside the RPS plasma tube to $n_i(L) = 5.1 \times 10^3\text{ cm}^{-3}$ at the wafer surface, effectively eliminating ion-assisted etching.

GAA NanoSheet Release Etching and Inner Spacer Cavity Recess

In 3nm/2nm Gate-All-Around (GAA) NanoSheet architectures, isotropic $SiGe$ recess etching defines the inner spacer cavities with sub-nanometer precision.

Selective dry isotropic etching recesses $Si_{0.70}Ge_{0.30}$ sacrificial layers by $15\text{ nm}$ to form inner spacer cavities. Chemical selectivity $> 150:1$ limits silicon channel erosion to $< 0.2\text{ nm}$.

High chemical selectivity of $Si_{1-x}Ge_x$ relative to pure $Si$ in $CF_4/O_2$ or $NF_3/H_2$ remote plasmas is driven by the lower $Si-Ge$ bond dissociation energy ($3.12\text{ eV}$) compared to $Si-Si$ ($3.38\text{ eV}$) and the catalytic oxidation of germanium sites. The selectivity ratio $S_{\text{SiGe/Si}}$ scales exponentially with germanium fraction $x$: $$S_{\text{SiGe/Si}}(x) = \frac{R_{\text{SiGe}}}{R_{\text{Si}}} = S_0 \cdot \exp\left( \frac{\Delta E_{\text{act}} \cdot x}{k_B T} \right)$$ For $x = 0.30$ ($Si_{0.70}Ge_{0.30}$) at $T = 320\text{ K}$, $\Delta E_{\text{act}} = 0.14\text{ eV}$, yielding $S_{\text{SiGe/Si}} = 1.0 \cdot \exp(0.14 / 0.02757) = \exp(5.07) = 160.4$. This $160:1$ selectivity ensures that etching a $15\text{ nm}$ lateral $SiGe$ recess results in a silicon channel thickness reduction of only $\Delta t_{\text{Si}} = 15\text{ nm} / 160.4 = 0.093\text{ nm}$ ($< 1\ \text{\AA}$), preserving nanosheet mechanical stability.

Isotropic Thermal Atomic Layer Etching (ALE) Reaction Cycles

Thermal isotropic atomic layer etching (ALE) uses sequential self-limiting gas-surface reaction steps to remove precise atomic layers without ion bombardment.

Thermal isotropic ALE proceeds via sequential fluorination (HF) and ligand exchange ($Al(CH_3)_3$), removing exactly $0.82\text{ \AA}$ of $Al_2O_3$ per cycle with $100\%$ self-limiting saturation.

The self-limiting saturation kinetics of thermal isotropic ALE per cycle is governed by the Langmuir adsorption isotherm for surface site coverage $\theta_{\text{sat}}$: $$\theta_{\text{sat}}(t_{\text{dose}}) = 1 - \exp\left( -S_0 \cdot \frac{P_{\text{dose}}}{\sqrt{2\pi m k_B T}} t_{\text{dose}} \right)$$ where $S_0 = 0.15$ is initial sticking probability, $P_{\text{dose}} = 1.0\text{ Torr}$ is precursor pressure, and $t_{\text{dose}}$ is exposure time. For $t_{\text{dose}} \ge 0.5\text{ s}$, $\theta_{\text{sat}} > 0.998$, ensuring $100\%$ self-limitation. The resulting thickness removed per cycle (Etch Per Cycle, EPC) is strictly quantized: $$EPC = \theta_{\text{sat}} \cdot d_{\text{monolayer}} = 0.998 \cdot (0.83\text{ \AA}) = 0.828\text{ \AA/cycle}$$ This atomic-scale quantization eliminates microloading, aspect-ratio-dependent rate decay, and pattern-dependent CD variations across complex 3D transistor architectures.

Metrology, Selectivity Qualification, and Damage-Free Interface Control

Qualification of isotropic processes combines inline spectroscopic ellipsometry, HR-TEM, AFM surface roughness metrology, and automated electrical MOS capacitor testing.

Interface state density $D_{\text{it}}$ following remote plasma isotropic processing is measured via high-frequency ($1\text{ MHz}$) and quasi-static MOS capacitance-voltage ($C-V$) profiling: $$D_{\text{it}} = \frac{C_{\text{ox}}}{e^2} \left( \frac{C_{\text{qs}} / C_{\text{ox}}}{1 - C_{\text{qs}} / C_{\text{ox}}} - \frac{C_{\text{hf}} / C_{\text{ox}}}{1 - C_{\text{hf}} / C_{\text{ox}}} \right)$$ Because remote plasma isotropic etching delivers zero energetic ions to the wafer, $D_{\text{it}}$ remains below $1.0 \times 10^{10}\text{ eV}^{-1}\text{cm}^{-2}$, matching pristine thermal oxide controls.

Combining atomic-resolution HR-TEM cross sections, AFM surface roughness mapping ($R_a < 0.15\text{ nm}$), and $C-V$ interface trap profiling confirms that remote plasma isotropic etching and thermal ALE provide the ultimate damage-free processing standard for sub-2nm transistor manufacturing.