Jitter is the timing uncertainty of a signal edge relative to its ideal position. In a digital or mixed-signal system, that uncertainty matters because it shrinks eye opening, reduces timing margin, and can turn a clean waveform into a marginal one. Jitter is one of the core problems of signal integrity because it is not just about voltage; it is about when the voltage arrives.
There are several ways to think about jitter. Period jitter describes the variation of an edge from cycle to cycle. Cycle-to-cycle jitter captures the difference between adjacent periods. Total jitter combines random and deterministic effects and is often what matters when you ask whether a link will pass a receiver threshold. In practice, a designer wants to know the jitter budget, the source of the error, and the path to reduce it.
Jitter usually comes from a mix of noise sources. PLL phase noise, crosstalk, power-supply ripple, reference noise, and intersymbol interference can all contribute. In high-speed links, even a small amount of jitter can produce a large bit-error penalty, so it is often treated as a first-order design constraint alongside loss and reflection.
| Jitter type | What it measures | Why it matters |
|---|---|---|
| Period jitter | Variation in each clock period | Impacts timing margin directly |
| Cycle-to-cycle jitter | Difference between adjacent periods | Exposes short-term instability |
| Total jitter | Combined random and deterministic error | Sets real-world link robustness |
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
<rect width="760" height="470" fill="#061018"/>
<rect x="24" y="24" width="712" height="422" rx="18" fill="#101b28" stroke="#51677d" stroke-width="1.2"/>
<text x="380" y="62" fill="#f4f7fb" font-size="20" font-weight="700" text-anchor="middle">Signal Integrity Jitter</text>
<text x="380" y="86" fill="#8ca3b8" font-size="12" text-anchor="middle">timing variation erodes margin and closes the eye</text>
<rect x="120" y="130" width="520" height="210" rx="12" fill="#121d2b" stroke="#60798f"/>
<path d="M160 320 C220 255, 290 240, 350 260 S480 305, 600 250" stroke="#8bd3ff" stroke-width="3" fill="none"/>
<path d="M160 320 C220 265, 290 250, 350 270 S480 315, 600 260" stroke="#34d399" stroke-width="3" fill="none"/>
<path d="M160 320 C220 275, 290 260, 350 280 S480 325, 600 270" stroke="#fbbf24" stroke-width="3" fill="none"/>
<line x1="160" y1="320" x2="600" y2="320" stroke="#8ca3b8" stroke-width="2"/>
<text x="190" y="170" fill="#8bd3ff" font-size="11">Ideal edge</text>
<text x="285" y="205" fill="#34d399" font-size="11">Actual edge</text>
<text x="430" y="245" fill="#fbbf24" font-size="11">Spread</text>
<rect x="140" y="360" width="480" height="40" rx="8" fill="#0e1722" stroke="#5d7488"/>
<text x="380" y="385" fill="#8ca3b8" font-size="10" text-anchor="middle">jitter reduces timing margin and makes the receiver decision less reliable</text>
</svg>
For a real channel or clock network, jitter is usually evaluated with eye diagrams, timing histograms, and phase-noise plots so the team can see whether the implementation is robust or just barely passing.
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.