A junctionless transistor replaces the graded, abruptly doped source-channel-drain structure of a conventional MOSFET with a single, uniformly and heavily doped nanowire or nanosheet running from source to drain, so that no physical junction — and no doping gradient — exists anywhere along the current path. The gate does not invert a lightly doped body to form a conduction channel the way an inversion-mode device does; instead it depletes the heavily doped body of majority carriers from the outside in, pinching off conduction in the OFF state through volume depletion, and in the ON state the full cross-section of the nanowire or sheet conducts as a bulk resistor rather than through a thin surface inversion layer. This single structural simplification removes the ultra-shallow-junction formation and abrupt-gradient control that become nearly impossible to achieve reliably as gate lengths scale below roughly 15 nm, but it introduces its own penalties: heavy uniform doping raises impurity scattering and series resistance, gate work function must be tuned with unusual precision to achieve full depletion at a usable threshold voltage, and channel thickness control becomes the dominant lever for turning the device off cleanly rather than a secondary parameter.

Volume depletion is the electrostatic mechanism that distinguishes a junctionless transistor from every inversion-mode device that came before it. Because the nanowire or nanosheet body is doped uniformly at a heavy concentration, typically near 1×10¹⁹ cm⁻³ for an n-type device, the gate must deplete the entire cross-section — not just form a thin inversion layer at the surface — before the channel stops conducting, so the depletion width has to sweep completely through a body that is commonly only 5 to 10 nm thick. This is why channel thickness, not gate length alone, sets whether a given junctionless design can reach a usable OFF-state at all.

Eliminating the source-drain junction removes one of the hardest lithographic and thermal challenges in scaled CMOS. A conventional inversion-mode MOSFET needs an ultra-shallow junction with a doping gradient steep enough to keep short-channel effects under control, typically requiring implant energies and rapid or laser anneals tuned to activate dopants without letting them diffuse laterally into the channel; a junctionless device needs none of this; because the doping is uniform end to end, there is no gradient to control and no junction depth to hit, which removes an entire class of implant and anneal process steps from the flow.

Heavy, uniform doping is also the source of the junctionless device's central penalty: elevated series resistance from impurity scattering. Carrier mobility in a heavily doped body running near 1×10¹⁹ cm⁻³ is measurably lower than in the lightly doped channel of an inversion-mode device, commonly by 20 to 30 percent at comparable gate length, because ionized-impurity scattering increases with dopant density across the entire conduction path rather than being confined to a thin surface layer. This mobility penalty is why junctionless designs typically show lower ON-current than an equivalent inversion-mode GAA device at the same supply voltage.

Threshold-voltage control in a junctionless device is dominated by doping concentration and body-thickness variation rather than by gate-length variation, inverting the sensitivity ranking familiar from inversion-mode design. A 5 percent variation in doping concentration or a half-nanometer variation in body thickness can shift Vt by tens of millivolts, whereas the same percentage variation in gate length has a comparatively muted effect once the device is short-channel-controlled by a wrapped gate; this reordering of sensitivities forces process teams to prioritize dose uniformity and thickness metrology ahead of the lithographic overlay budgets that dominate inversion-mode Vt control.

Subthreshold swing and drain-induced barrier lowering remain governed by the same gate-electrostatics rules that apply to any gate-all-around device, regardless of whether the channel is junctionless or inversion-mode. A wrapped gate with an EOT near 1.2 nm still targets subthreshold swing below roughly 70 mV/decade and DIBL below 30 mV/V in a well-controlled junctionless nanowire, because the wrap-around geometry — not the doping profile — is what suppresses short-channel electrostatic leakage paths; doping uniformity changes how the channel turns off, not how well the gate controls the channel geometrically. $V_t \approx \Phi_m - \Phi_s + \frac{qN_Dt_{si}^2}{8\varepsilon_{si}}$ captures how the full-depletion threshold voltage depends jointly on gate work function, doping concentration, and body thickness squared, a dependence with no direct analogue in a lightly doped inversion-mode channel.

junctionless fabrication flow ──▶ dose-uniform nanowire integration
  nanowire/nanosheet patterning (hard-mask etch)
       │      5-10 nm target body thickness
       │
       ├─▶ single uniform dopant implant, no S/D mask split
       │      ≈1e19 cm⁻³ target dose, n-type or p-type
       │
       ├─▶ dopant activation anneal (msec-scale, low thermal budget)
       │      no lateral diffusion control needed — no gradient to preserve
       │
       ├─▶ gate stack deposition, work function tuned near midgap
       │      Φm ≈4.5 eV target, EOT ≈1.2 nm
       │
       ├─▶ full gate-all-around wrap for volume depletion control
       │      subthreshold swing target <70 mV/decade
       │
       └─▶ contact formation directly on uniformly doped body
              no S/D epitaxy step required

Removing the source-drain epitaxy and abrupt-junction anneal steps shortens the junctionless process flow relative to a comparable inversion-mode nanosheet. Because the same doping level extends under the contacts as under the gate, there is no separate source/drain epitaxial regrowth step and no requirement for a high-temperature anneal dedicated to activating an abrupt gradient without letting it diffuse; the dopant activation step can instead run at a lower thermal budget, commonly a millisecond-scale laser or flash anneal rather than a multi-second rapid thermal anneal near 1000 °C, which reduces total thermal exposure for the rest of the stack.

Series resistance and contact engineering absorb part of the ON-current penalty and are treated as a co-design problem with the doping level itself. A specific contact resistivity target below roughly 1×10⁻⁹ Ω·cm² is still expected of a junctionless contact stack, so foundries lean on the same low-resistance metal fills — ruthenium and cobalt among them — being qualified for conventional GAA nanosheets, while also raising the channel doping level modestly above the volume-depletion minimum where the thickness window allows, trading a small increase in OFF-state leakage margin for a reduction in ON-state series resistance.

Gate-induced drain leakage is markedly reduced in a junctionless device precisely because there is no abrupt drain junction to generate the band-to-band tunneling current that drives GIDL in inversion-mode devices. A conventional MOSFET's GIDL current originates at the high-field overlap region between gate and drain junction, where the abrupt doping transition creates a narrow, heavily band-bent region favorable to tunneling; a junctionless channel has no such transition under the gate-drain overlap, so GIDL in published junctionless comparisons commonly runs an order of magnitude or more below an equivalent inversion-mode device at the same OFF-state bias.

Multi-threshold-voltage library construction is harder in a junctionless flow than in an inversion-mode HKMG flow, because doping concentration and body thickness are coarser, harder-to-vary knobs than a stack of independently deposited work-function metals. An inversion-mode process can offer several Vt flavors by swapping thin metal or cap layers late in the flow with minimal impact on the rest of the process, whereas a junctionless process would need distinct implant doses or distinct nanowire thicknesses per flavor, each requiring its own patterning and implant mask, which pushes most current junctionless work toward single- or dual-Vt libraries rather than the four-or-more-flavor libraries common in advanced inversion-mode nodes.

Junctionless devices concentrate at the most deeply scaled gate lengths, where conventional abrupt-junction formation approaches its physical limits rather than being a matter of process refinement. Below roughly 10 to 12 nm physical gate length, the doping gradient needed for an inversion-mode source-drain junction must fall within a distance comparable to the gate length itself, which strains implant and anneal control past what is comfortably manufacturable; a junctionless channel sidesteps this specific limit entirely by never needing a gradient in the first place, even though it must then solve the separate, and different, problem of full-body depletion control.

Every advantage and every penalty of the junctionless architecture traces back to the same single design decision: one uniform doping level from source to drain, with no junction anywhere. The advantage — no abrupt gradient to control, fewer implant and anneal steps, a lower thermal budget suited to 3D integration — and the penalty — reduced mobility, elevated series resistance, a narrower multi-Vt design space, and Vt sensitivity dominated by doping and thickness rather than gate length — are two faces of the identical structural choice. Read junctionless transistors through a coupled-systems lens: the doping level, the body thickness, the gate work function, and the resulting Vt and ON-current all move together as one interdependent system, so a change intended to fix any single metric — raising the dose to cut resistance, thinning the body to improve depletion, shifting the work function to hit a Vt target — inevitably reshapes the other three, and a junctionless design is only sound when all four are qualified as a set rather than tuned one at a time.

Appendix: Process Control and Metrology Reference

Dopant concentration metrology for a junctionless body relies on techniques capable of resolving a uniform profile inside a nanowire or nanosheet only a few nanometers thick. Secondary-ion mass spectrometry provides bulk dose confirmation on blanket monitor wafers, while atom-probe tomography and scanning capacitance microscopy are used in development to confirm that the doping profile inside a patterned nanowire stays flat within the body rather than showing unintended pile-up near the surface, since a hidden gradient defeats the junctionless premise even if the average dose is correct.

Qualification of a junctionless implant and activation recipe runs across many lots before release to production, mirroring the qualification discipline used for any new doping module. A candidate dose and anneal combination is evaluated for Vt mean and spread, ON-current, and leakage across dozens of wafers spanning multiple lots, because a recipe with an acceptable average dose but excessive lot-to-lot spread will surface as Vt mismatch only after volume ramp, not during early characterization on a handful of wafers.

Academic groups at MIT, Stanford, and UC Berkeley continue to study alternative channel materials and doping techniques aimed at recovering some of the mobility lost to heavy uniform doping. Work on strained silicon channels, alternative dopant species with reduced scattering cross-sections, and non-implant doping techniques such as monolayer-doping periodically feeds new candidate process options into foundry and equipment-vendor evaluation pipelines, motivated by the same mobility-versus-depletion tradeoff that has defined the junctionless architecture since its earliest device demonstrations.