Killer defect size

Keywords: killer defect size,metrology

Killer defect size is the minimum defect dimension that causes device failure — a critical threshold that determines inspection sensitivity requirements, with smaller nodes requiring detection of ever-tinier defects as feature sizes shrink and defect tolerance decreases.

What Is Killer Defect Size?

- Definition: Smallest defect that impacts device functionality or yield.
- Measurement: Typically expressed as percentage of minimum feature size.
- Rule of Thumb: ~30-50% of critical dimension (CD).
- Node Dependence: Shrinks with each technology generation.

Why Killer Defect Size Matters

- Inspection Sensitivity: Determines required detection capability.
- Cost: Smaller defects require more expensive inspection tools.
- Throughput: Higher sensitivity often means slower inspection.
- Nuisance Rate: Detecting smaller defects increases false positives.
- Yield Impact: Missing killer defects directly reduces yield.

Scaling with Technology Node

``
Node Min Feature Killer Defect Size
180nm 180nm 60-90nm
90nm 90nm 30-45nm
45nm 45nm 15-23nm
22nm 22nm 7-11nm
7nm 7nm 2-4nm
3nm 3nm 1-2nm
`

Defect Types and Criticality

Particles: Size relative to line width determines if it causes shorts or opens.
Scratches: Width and depth determine if metal lines are severed.
Voids: Size relative to via diameter determines resistance increase.
Bridging: Gap closure distance determines if short circuit forms.

Determination Methods

Electrical Testing: Correlate defect sizes with electrical failures.
Simulation: Model defect impact on device performance.
Design Rules: Calculate from minimum spacing and width rules.
Historical Data: Learn from previous generation yield data.
Accelerated Testing: Intentionally introduce defects of varying sizes.

Quick Calculation

`python
def calculate_killer_defect_size(technology_node, layer_type):
"""
Estimate killer defect size for a given node and layer.

Args:
technology_node: Feature size in nm (e.g., 7 for 7nm)
layer_type: 'metal', 'poly', 'contact', 'via'

Returns:
Killer defect size in nm
"""
# Typical ratios
ratios = {
'metal': 0.4, # 40% of line width
'poly': 0.35, # 35% of gate length
'contact': 0.5, # 50% of contact diameter
'via': 0.5 # 50% of via diameter
}

critical_dimension = technology_node
ratio = ratios.get(layer_type, 0.4)

killer_size = critical_dimension * ratio

return killer_size

# Example
node_7nm_metal = calculate_killer_defect_size(7, 'metal')
print(f"7nm metal killer defect: {node_7nm_metal:.1f}nm")
# Output: 7nm metal killer defect: 2.8nm
`

Layer-Specific Considerations

Metal Layers: Particles can cause shorts between lines or opens in lines.
Poly/Gate: Defects affect transistor performance and leakage.
Contact/Via: Voids increase resistance, particles cause shorts.
STI: Defects can cause leakage between devices.

Inspection Capability

Optical Inspection: Limited to ~100nm+ defects (wavelength limited).
E-beam Inspection: Can detect 10-30nm defects (slower, expensive).
SEM Review: Sub-nm resolution for detailed analysis.
Scatterometry: Indirect detection through optical signatures.

Economic Trade-offs

`
Smaller Detection → Higher Cost + Lower Throughput
Larger Detection → Lower Cost + Higher Throughput + Missed Defects

Optimal: Detect killer defects with acceptable cost and speed
``

Best Practices

- Layer-Specific Thresholds: Different killer sizes for different layers.
- Electrical Correlation: Validate killer size with test data.
- Sampling Strategy: Full inspection for critical layers, sampling for others.
- Tool Selection: Match inspection capability to killer defect size.
- Continuous Monitoring: Track defect size distribution over time.

Advanced Concepts

Probabilistic Killer: Defect has probability of causing failure based on size.
Context-Dependent: Same defect size may be killer in one location, nuisance in another.
Multi-Defect Interaction: Multiple sub-killer defects can combine to cause failure.
Latent Defects: Sub-killer defects that grow or cause reliability failures.

Typical Values

- Logic 7nm: 2-4nm killer defect size.
- DRAM 1x nm: 3-5nm killer defect size.
- 3D NAND: 5-10nm killer defect size (larger features).
- Mature Nodes (>28nm): 10-50nm killer defect size.

Killer defect size is the fundamental limit for inspection — as nodes shrink, the challenge of detecting ever-smaller defects while maintaining throughput and managing nuisance rates becomes increasingly difficult, driving innovation in inspection technology and methodology.

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