KOH etching is crystal-programmed silicon machining: hydroxide chemistry supplies removal, but wafer orientation, mask azimuth, plane-rate ratios, corner evolution, hydrogen-bubble transport, mask integrity, etch-stop choice, bath history, and potassium control determine the final three-dimensional structure.

KOH etch is an aqueous potassium-hydroxide process that converts silicon crystal orientation into three-dimensional geometry. Hydroxide reacts rapidly with many exposed silicon planes but much more slowly with the densely bonded {111} family. On a (100) wafer, a mask opening aligned to the crystal axes therefore evolves into sloped {111} sidewalls at 54.74° to the surface; opposing planes can meet to form a V-groove or pyramidal cavity. This is crystallographic anisotropy—not directional ion bombardment—and it is why KOH remains useful for MEMS cavities, diaphragms, optical alignment grooves, microfluidics, and wafer-level mechanical structures.

The chemistry removes silicon and evolves hydrogen. A simplified net representation is

Si + 2KOH + H₂O → K₂SiO₃ + 2H₂↑,

although the liquid contains hydroxide, hydrated silicate species, potassium ions, and intermediate surface states rather than a single elementary reaction. Hydroxide initiates attack at accessible silicon back-bonds, water participates in oxidation and dissolution, soluble silicate enters the bath, and molecular hydrogen leaves the surface. Those bubbles are a process variable: if they adhere to a cavity or mask edge, they locally block liquid access and print roughness or residual silicon.

The wafer cut and mask azimuth define the profile before the wafer reaches chemistry. On (100) silicon, square or rectangular openings aligned to ⟨110⟩ directions expose four slow {111} walls and produce pyramidal or V-shaped boundaries. A long line opening forms a V-groove whose ideal depth when opposing {111} walls meet is approximately opening width divided by √2. On (110) silicon, selected {111} planes can stand nearly vertical, enabling deep trenches with very different plan-view constraints. Wafer flat or notch tolerance, lithography rotation, mask-edge direction, and crystal miscut all contribute to final geometry.

Slow planes are not absolute etch stops. Their rate is much lower than that of faster planes, but it is not zero and the plane-rate ratio changes with temperature, KOH concentration, dissolved silicon, impurities, and additives. A long over-etch can recess or roughen the nominal {111} boundary. Local defects, damage, dopant gradients, crystal defects, and mask leakage can also disrupt the ideal faceted shape. Design rules must use measured plane rates and corner behavior from the qualified bath, not a perfect geometric model alone.

Concave and convex corners behave differently. Concave intersections can terminate on stable slow planes, while convex corners expose fast-etch planes and retreat laterally. Uncompensated outside corners therefore round or disappear during a deep etch. Corner-compensation beams, triangles, serifs, or sacrificial structures deliberately supply silicon that can be consumed before the intended corner is reached. The compensation dimension is coupled to depth, time, orientation, and actual fast-plane rate, so copying a generic serif is rarely sufficient.

Concentration and temperature jointly set rate, roughness, and mask budget. KOH processes span a broad range of aqueous concentrations and commonly operate at elevated temperature. Raising temperature accelerates reaction kinetics and can increase sensitivity to thermal gradients, mask stress, evaporation, and bubble behavior. Changing concentration alters hydroxide activity, water availability, silicon solubility, plane-rate ratios, and surface morphology. The fastest blanket (100) rate is not necessarily the best production point; a slower condition may deliver smoother {111} walls, stronger selectivity, or more stable corner geometry.

Additives and bath history can be as important as nominal KOH percentage. Isopropyl alcohol or qualified surfactants are sometimes used to change wetting, bubble release, roughness, and plane rates, but they also change vapor loading, flammability controls, replenishment behavior, and downstream contamination. Silicon dissolved from preceding wafers changes the bath’s chemical state. Carbonate enters through exposure to air, water evaporates, drag-out removes solute, and incoming rinse water dilutes the tank. Make-up recipe, cover state, feed-and-bleed policy, lot loading, idle control, and replacement criteria belong in the specification.

Mask integrity is a first-order yield variable. LPCVD silicon nitride is often selected for long KOH exposure because its resistance is much stronger than that of common photoresists. Thermal oxide can work for shorter or qualified windows but must carry enough thickness to survive the full etch and over-etch. Pinholes become deep pits; mask cracks become trenches; poor backside coverage can thin the entire wafer; and bevel or edge exposure can initiate chipping. Mask deposition stress, pattern etch damage, pre-clean, backside handling, and edge exclusion must be checked together.

Metals sharply constrain process placement. KOH attacks aluminum and is incompatible with many exposed metals, adhesion layers, and finished device stacks. Potassium is also a mobile ionic contaminant of concern in semiconductor fabrication. For those reasons, KOH bulk micromachining is often performed before sensitive metallization or in segregated MEMS equipment with dedicated carriers and contamination controls. A “silicon-only” cavity can still expose front-side bond pads through pinholes, wafer edges, alignment marks, or protection-layer defects, so the complete wafer map must be reviewed.

Etch-stop selection determines thickness accuracy. A purely timed etch inherits incoming wafer-thickness variation, rate drift, and temperature/load variation. Geometric self-termination occurs when slow crystal planes meet, but only for compatible opening shapes and target depths. Heavy boron doping can suppress silicon etching and define a p⁺ membrane, while electrochemical p–n junction stops use an applied potential to distinguish regions. SOI provides a buried-oxide stop with precise device-layer thickness. Each option trades process complexity, residual stress, electrical compatibility, and stop-layer attack.

Backside diaphragm etching illustrates the complete tolerance chain. The final membrane thickness is wafer thickness minus cavity depth, so a few micrometers of starting-wafer variation can dominate a thin target. Backside lithography placement sets the lateral cavity position relative to front-side piezoresistors, electrodes, or proof masses. The sloped {111} walls expand the front-side footprint beyond the mask opening, and convex-corner loss changes stress concentration. Double-side alignment, total-thickness variation, bow, mask bias, crystal orientation, rate, and stop strategy must all enter the mechanical design model.

Hydrogen management separates smooth etching from bubble-printed defects. Wafer orientation, feature direction, cassette spacing, agitation, bath circulation, and compatible wetting aids affect whether bubbles detach or remain trapped. Strong stirring can improve transport but distort local temperature or damage fragile membranes; weak flow can create stagnant cavities. Face-down, vertical, or tilted processing changes both bubble escape and particulate settling. The qualified module specifies entry angle, wafer orientation, motion, and load configuration rather than treating agitation as an informal operator choice.

Surface morphology diagnoses different mechanisms. Pyramidal hillocks can arise when particles, hydrogen bubbles, reaction products, mask fragments, or local micromasks shield fast-etch planes. Striations may trace flow, orientation error, or crystal defects. Large pits implicate mask pinholes or particle contamination; edge trenches implicate bevel protection; nonuniform depth implicates temperature, concentration, loading, or access. Roughness should be measured on the plane that matters to the device—an optical {111} wall, diaphragm backside, bonding surface, or fluidic channel—not only on a blanket (100) monitor.

Rinsing must remove both caustic liquid and soluble products. Lift speed and drain time contribute additional exposure, especially on deep features. Prompt, high-flow DI-water dilution stops reaction and clears potassium and silicate residue. Directly mixing strong acid into concentrated KOH is unsafe and can generate intense heat; neutralization belongs in engineered waste handling, not on the wafer. Multi-stage overflow or quick-dump rinses, megasonic limits, drying orientation, and residue metrology should be matched to cavity depth and membrane fragility.

KOH, TMAH, DRIE, and vapor etches solve different integration problems. TMAH also provides crystal-plane anisotropy and is often considered where potassium contamination is unacceptable, but its toxicity, rate, roughness, and material compatibility require an independent process window. Bosch DRIE makes deep profiles largely independent of crystal orientation and supports near-vertical arbitrary layouts, at the cost of plasma damage, scallops, mask demand, and equipment complexity. XeF₂ vapor etches silicon isotropically with high selectivity to many materials and is useful for release, but it does not create crystallographic facets. Geometry and stack compatibility choose the method.

Hot concentrated KOH is a severe caustic service. Tanks, heaters, probes, filters, pumps, plumbing, valves, cassettes, lids, and exhaust components require qualified materials and temperature ratings. Heater and level interlocks prevent dry firing; covers and local exhaust control aerosol; secondary containment and leak detection limit releases. Chemical additions must control splash and heat of dilution. Site-specific PPE, transfer procedures, emergency showers, exposure response, waste segregation, and training are inseparable from repeatable process operation.

Production qualification connects bath state to three-dimensional evidence. Track KOH make-up, concentration measurement, temperature trajectory, water and additive replenishment, exposed silicon area, dissolved-silicon proxy, carbonate or aging indicator, wafer count, filter state, and bath age. Correlate these with plane-specific rate, cavity depth, membrane thickness, sidewall angle, convex-corner loss, roughness, mask loss, within-wafer uniformity, particles, potassium residue, and device performance. Cross sections and profilometry are essential because blanket thickness removal cannot reveal faceting or undercut.

A transferable KOH recipe is an orientation-aware geometry model backed by bath controls. It specifies wafer cut and miscut, layout azimuth, mask stack, starting thickness, plane rates, corner compensation, stop mechanism, bath composition and age, temperature recovery, load, bubble-management motion, withdrawal, rinse, and metrology. When those elements agree, the silicon crystal acts as a precise fabrication tool. When they do not, a familiar beaker chemistry can produce large dimensional errors that no timer adjustment can rescue.

Following KOH from surface reaction and hydrogen evolution through crystal-plane geometry, corner compensation, mask survival, bath history, and membrane metrology is the kind of chemistry-to-design connection Chip Foundry Services makes explicit—turning anisotropic silicon etching into a manufacturable three-dimensional process.

Start=>start: Orientation-verified masked silicon wafer
Check=>condition: Mask, bath, temperature, load, exhaust, and contamination controls pass?
Prewet=>operation: Prewet; immerse with qualified azimuth and motion
Etch=>operation: Etch while managing H₂ bubbles and bath state
Stop=>condition: Geometric, doped, junction, SOI, or timed endpoint reached?
Rinse=>operation: Controlled withdrawal and multi-stage DI rinse
Dry=>operation: Dry without membrane collapse or residue
Verify=>condition: Depth, angle, membrane, corners, roughness, and K⁺ pass?
Release=>end: Release lot and update plane-rate model
Hold=>end: Hold; contain and investigate
Start->Check
Check(yes)->Prewet->Etch->Stop
Check(no)->Hold
Stop(no)->Etch
Stop(yes)->Rinse->Dry->Verify
Verify(yes)->Release
Verify(no)->Hold

Read KOH silicon etching through a crystal-plane kinetics, three-dimensional layout, bubble-transport, and etch-stop integration lens rather than a timed anisotropic silicon bath lens.

Crystal Geometry and Orientation-Aware Layout

The angle between (100) and {111} planes is $\arccos(1/\sqrt3)=54.74°$. A long opening of width $W$ aligned to ⟨110⟩ on a (100) wafer forms an ideal V-groove whose slow walls meet at $d=W/(2\tan54.74°)\approx0.354W$. A 100 µm opening therefore closes near 35.4 µm depth; a 500 µm opening closes near 176.8 µm. Finite {111} rate, mask recession, miscut, and alignment error modify those values.

On a (110) wafer, selected {111} planes can be nearly vertical, enabling deep crystallographic trenches but imposing a different plan-view rule set. The wafer notch, crystal miscut, lithography rotation, mask-edge roughness, and double-side alignment propagate into cavity position and wall angle. CAD must encode crystallography before tapeout rather than treating KOH as a generic vertical subtractive step.

Isopropyl alcohol or surfactants may improve wetting and bubble release, but also change plane rates, vapor loading, flammability, exhaust, contamination, and replenishment. Additives must be treated as controlled chemical components. A covered bath reduces evaporation and carbonate uptake; feed-and-bleed stabilizes some variables but does not remove all contaminants.

Mask Survival, Corners, and Etch Stops

LPCVD nitride is commonly used for long KOH exposures; oxide may suffice for shorter windows. Required mask thickness is total equivalent silicon removal divided by silicon-to-mask selectivity plus incoming variation, pinhole risk, stress cracking, bevel exposure, and minimum residual thickness. A single pinhole can become a deep pyramidal pit; a backside edge leak can thin or fracture an entire wafer.

Timed depth inherits wafer-thickness variation and rate drift. Geometric closure is precise only for compatible openings. Heavy boron doping can strongly suppress rate but introduces junction depth, stress, diffusion, and device constraints. Electrochemical stops use a biased p–n junction. SOI buried oxide gives a physical stop and device-layer thickness but adds BOX attack and edge-access budgets.

Bath history follows exposed silicon area and depth, not count alone. Dissolved silicate, carbonate, evaporative concentration, DI drag-in, additive loss, and contaminants shift rate and morphology. A material balance records KOH and water additions, drag-out, estimated silicon removal, temperature hours, cover state, and feed/bleed. Filtration removes suspended particles but not dissolved potassium, silicate, or carbonate.

Rinse, Potassium Control, and Process Alternatives

Withdrawal and drain time add etch. Prompt DI dilution stops hydroxide attack and removes soluble silicate and $K^+$. Strong acid must never be mixed directly into concentrated KOH on the wafer; neutralization belongs in engineered waste handling because it is highly exothermic. Deep cavities require multiple rinse exchanges, and outlet conductivity alone may miss trapped residue.

Potassium is a mobile ionic contaminant, so KOH is often segregated from CMOS lines and scheduled before metals. Dedicated tanks, cassettes, carriers, metrology paths, and waste systems prevent cross-contamination. TXRF, ion chromatography, surface analysis, and electrical mobile-ion monitors verify the handoff. Aluminum and many metals are incompatible; the full wafer, bevel, backside, and alignment structures must be audited.

Hot concentrated KOH causes severe chemical and thermal burns. Qualified tanks, heaters, probes, pumps, valves, cassettes, exhaust, secondary containment, leak detection, level and over-temperature interlocks, compatible drains, PPE, emergency showers, and site-specific response are mandatory. Chemical dilution and waste neutralization are engineered operations; only trained personnel may operate or service the module.

Equipment from SCREEN, Tokyo Electron, Lam Research, and Applied Materials differs in flow, cassette motion, dosing, and thermal architecture. Intel, TSMC, Samsung, Bosch, STMicroelectronics, Analog Devices, and MEMS foundries may use distinct proprietary windows, but all must close the same crystal geometry, bath state, bubble, mask, stop, contamination, rinse, and EHS constraints.

The transferable KOH recipe is an orientation-aware model plus a controlled state machine: wafer cut and miscut, mask azimuth, plane rates, corners, stop, mask stack, concentration, temperature, additives, bath age, exposed silicon, load, bubble motion, endpoint, withdrawal, rinse, dry, metrology, contamination, fault response, and safety approval.