Process Design Kit (PDK) is the complete package of files, models, and rules that a foundry delivers to chip designers so they can design circuits that will manufacture correctly on that process node — it is the contract between fabrication and design. A PDK contains SPICE transistor models (BSIM-CMG, PSP), standard-cell and I/O libraries characterized across PVT corners, technology LEF files defining metal-stack geometry, design-rule-check (DRC) decks, layout-versus-schematic (LVS) netlists, parasitic extraction (PEX) rules, electromigration limits, and reliability models. Without a PDK, a designer cannot simulate, lay out, verify, or tape out a chip. Every CFS simulator — from the Transistor sim at /transistor to the Interconnect sim at /interconnect — models the same physics that PDK characterization captures.
What's inside a PDK — the file taxonomy:
| Component | Format | Purpose | Who consumes it |
|---|---|---|---|
| SPICE models (transistor) | BSIM-CMG / PSP / HiSIM | I-V, C-V, noise, mismatch for all device flavors | Circuit simulators (Spectre, HSPICE, Xyce) |
| Standard-cell library | Liberty (.lib) + LEF + GDS | Pre-characterized gates/FFs with timing, power, noise | Synthesis (Genus/DC), PnR (Innovus/ICC2) |
| I/O library | Liberty + GDS + IBIS | I/O pad cells (ESD, driver, receiver) | Top-level integration |
| Technology LEF | LEF (Cadence format) | Metal/via layers, pitches, widths, spacing rules | Place-and-route tools |
| DRC rule deck | Calibre SVR / ICV / Pegasus | Geometric design rules (min width, spacing, enclosure) | Physical verification |
| LVS rule deck | Calibre / ICV / Pegasus | Netlist extraction + comparison to schematic | Physical verification |
| PEX rules | StarRC / QRC rule files | Parasitic R, C, L extraction from layout geometry | Timing sign-off (STA) |
| EM/IR rules | EM spec + PDN guidelines | Current-density limits per metal layer and via | Reliability sign-off |
| Reliability models | HCI, BTI, TDDB models | Aging/degradation over product lifetime | Reliability simulation |
| PCells / iPDK | Skill / Python / OpenAccess | Parameterized layout generators for custom devices | Analog/custom layout |
| Documentation | PDF + online | Design manual, process specs, known issues | All designers |
PDK corners — spanning the manufacturing window. Silicon fabrication has inherent variation: threshold voltage, oxide thickness, metal resistance, and capacitance all fluctuate across wafers and lots. The PDK provides pre-characterized models at multiple corners:
- Process: TT (typical-typical), FF (fast-fast NMOS/PMOS), SS (slow-slow), FS (fast-N/slow-P), SF (slow-N/fast-P).
- Voltage: Nominal ± 10% (e.g. 0.75V nominal → 0.675V / 0.825V).
- Temperature: −40°C (cold, fast), 25°C (room), 125°C (hot, slow — worst leakage).
A full sign-off requires running timing across the "worst-case corners": SS/low-V/125°C for setup, FF/high-V/−40°C for hold — and often 50+ additional Monte Carlo / AOCV statistical points for yield-aware closure.
SPICE models — the transistor contract. The foundry measures thousands of transistors across process splits, then fits the data to a compact model (BSIM-CMG for FinFET/GAA, PSP for planar). The model captures:
with 300–600 parameters per device flavor (NMOS/PMOS × SVT/LVT/HVT × multiple channel lengths). Accuracy target: <2% error vs measured silicon across the full bias range. Mismatch parameters ($A_{V_T}$, $A_{\beta}$) capture random dopant fluctuation for SRAM and analog yield.
The standard-cell library — pre-built logic. The PDK's cell library (see the CFS "standard cell" keyword) provides 500–2000 logic cells, each independently characterized by SPICE into Liberty tables across all PVT corners. The timing closure flow (synthesis → PnR → STA → ECO) operates entirely on these Liberty models — never on raw SPICE during physical design. Library quality (density, speed, leakage) directly determines the PPA (performance, power, area) achievable on the node.
DRC and LVS — the manufacturing contract. Design rules encode everything the fab can and cannot print:
- Minimum width (e.g. M1 min width = 14 nm at N3)
- Minimum spacing (metal-to-metal, poly-to-poly)
- Enclosure (via must be enclosed by metal on all sides by ≥ X nm)
- Density (metal density must be 20–80% in any 50 µm × 50 µm window for CMP uniformity)
- Antenna rules (maximum gate-to-metal-area ratio during etch to prevent plasma damage)
A modern DRC deck at 3 nm contains 3000–5000 individual rules. A single violation can cause a systematic yield loss across every die on the wafer.
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<text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">ASIC Physical Design — RTL to GDSII</text>
<text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">synthesize logic, place cells, route metal, verify DRC/LVS — the backend flow that makes silicon real</text>
<!-- === TOP: Physical design flow === -->
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<text x="76" y="110" fill="#c4b5fd" font-size="8" text-anchor="middle">RTL</text>
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<text x="173" y="107" fill="#93c5fd" font-size="7.5" text-anchor="middle">Synthesis</text>
<text x="173" y="118" fill="#6b7684" font-size="6.5" text-anchor="middle">gate netlist</text>
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<text x="270" y="107" fill="#6ee7b7" font-size="7.5" text-anchor="middle">Floorplan</text>
<text x="270" y="118" fill="#6b7684" font-size="6.5" text-anchor="middle">macro + IO</text>
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<text x="367" y="118" fill="#6b7684" font-size="6.5" text-anchor="middle">std cells</text>
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<text x="464" y="118" fill="#6b7684" font-size="6.5" text-anchor="middle">clock tree</text>
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<text x="658" y="107" fill="#f87171" font-size="7.5" text-anchor="middle">Signoff</text>
<text x="658" y="118" fill="#6b7684" font-size="6.5" text-anchor="middle">DRC/LVS/STA</text>
<text x="380" y="148" fill="#6b7684" font-size="8" text-anchor="middle">PDK (Process Design Kit) provides standard cells, tech rules, SPICE models, and metal stack definitions</text>
<!-- === MIDDLE LEFT: PDK and standard cells === -->
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<text x="200" y="183" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">PDK — Process Design Kit</text>
<text x="45" y="205" fill="#60a5fa" font-size="8.5" font-weight="600">Standard cells:</text>
<text x="145" y="205" fill="#8b98a5" font-size="8.5">NAND, NOR, INV, FF, MUX (pre-characterized)</text>
<text x="45" y="221" fill="#34d399" font-size="8.5" font-weight="600">Liberty (.lib):</text>
<text x="135" y="221" fill="#8b98a5" font-size="8.5">timing, power, noise for each cell/corner</text>
<text x="45" y="237" fill="#fbbf24" font-size="8.5" font-weight="600">LEF/DEF:</text>
<text x="110" y="237" fill="#8b98a5" font-size="8.5">physical dimensions, pin locations, metal rules</text>
<text x="45" y="253" fill="#c4b5fd" font-size="8.5" font-weight="600">DRC rules:</text>
<text x="120" y="253" fill="#8b98a5" font-size="8.5">min width, spacing, enclosure, density</text>
<text x="45" y="269" fill="#f87171" font-size="8.5" font-weight="600">SPICE models:</text>
<text x="140" y="269" fill="#8b98a5" font-size="8.5">BSIM4/BSIM-CMG for transistor simulation</text>
<text x="45" y="287" fill="#8b98a5" font-size="8">Corners: SS/TT/FF × 0.9V/1.0V/1.1V × -40/25/125°C</text>
<!-- === MIDDLE RIGHT: ASIC vs FPGA === -->
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<text x="562" y="183" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">ASIC vs FPGA Tradeoffs</text>
<text x="410" y="203" fill="#60a5fa" font-size="8.5" font-weight="600">ASIC</text>
<text x="410" y="219" fill="#8b98a5" font-size="8.5">+ 10-100× perf/watt vs FPGA</text>
<text x="410" y="235" fill="#8b98a5" font-size="8.5">+ lowest unit cost at volume</text>
<text x="410" y="251" fill="#f87171" font-size="8.5">- $5-50M NRE, 12-18mo design</text>
<text x="410" y="267" fill="#f87171" font-size="8.5">- no post-fab changes (mask-set fixed)</text>
<text x="590" y="203" fill="#34d399" font-size="8.5" font-weight="600">FPGA</text>
<text x="590" y="219" fill="#8b98a5" font-size="8.5">+ instant reprogramming</text>
<text x="590" y="235" fill="#8b98a5" font-size="8.5">+ $0 NRE, prototype in days</text>
<text x="590" y="251" fill="#f87171" font-size="8.5">- 10× more power per op</text>
<text x="590" y="267" fill="#f87171" font-size="8.5">- higher unit cost at scale</text>
<text x="562" y="289" fill="#fbbf24" font-size="8.5" text-anchor="middle">Crossover: ~50K-100K units/year (volume → ASIC wins)</text>
<!-- === BOTTOM: EDA tools === -->
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<text x="380" y="323" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">EDA Tool Landscape</text>
<text x="130" y="347" fill="#c4b5fd" font-size="9.5" text-anchor="middle" font-weight="600">Synopsys</text>
<text x="130" y="361" fill="#8b98a5" font-size="8" text-anchor="middle">Design Compiler, ICC2</text>
<text x="130" y="375" fill="#8b98a5" font-size="8" text-anchor="middle">PrimeTime, StarRC</text>
<text x="130" y="389" fill="#6b7684" font-size="7.5" text-anchor="middle">#1 market share</text>
<text x="310" y="347" fill="#fbbf24" font-size="9.5" text-anchor="middle" font-weight="600">Cadence</text>
<text x="310" y="361" fill="#8b98a5" font-size="8" text-anchor="middle">Genus, Innovus</text>
<text x="310" y="375" fill="#8b98a5" font-size="8" text-anchor="middle">Tempus, Quantus</text>
<text x="310" y="389" fill="#6b7684" font-size="7.5" text-anchor="middle">strong in P&R</text>
<text x="490" y="347" fill="#34d399" font-size="9.5" text-anchor="middle" font-weight="600">Siemens (Mentor)</text>
<text x="490" y="361" fill="#8b98a5" font-size="8" text-anchor="middle">Calibre (DRC/LVS)</text>
<text x="490" y="375" fill="#8b98a5" font-size="8" text-anchor="middle">Questa, HyperLynx</text>
<text x="490" y="389" fill="#6b7684" font-size="7.5" text-anchor="middle">#1 in signoff verify</text>
<text x="650" y="347" fill="#60a5fa" font-size="9.5" text-anchor="middle" font-weight="600">Open-source</text>
<text x="650" y="361" fill="#8b98a5" font-size="8" text-anchor="middle">OpenROAD, Yosys</text>
<text x="650" y="375" fill="#8b98a5" font-size="8" text-anchor="middle">Magic, KLayout</text>
<text x="650" y="389" fill="#6b7684" font-size="7.5" text-anchor="middle">SkyWater 130nm PDK</text>
<!-- Key insight -->
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<text x="380" y="425" fill="#fbbf24" font-size="9.5" text-anchor="middle">Physical design closes the gap between logic and manufacturing — timing, power, and area are decided here, not in RTL.</text>
<text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">Every transistor in every chip went through this flow — synthesis, place, route, signoff — billions of times over.</text>
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Open-source PDKs — democratizing chip design. Google/SkyWater's SKY130 (130 nm, 2020) and GlobalFoundries' GF180MCU (180 nm, 2022) are open PDKs freely available to anyone — enabling university research, startups, and open-source EDA tool development (OpenROAD, OpenLane, Magic, ngspice) without the NDA-gated access that foundry PDKs traditionally require. While these are mature nodes (not competitive for AI chips), they let designers learn the full RTL-to-GDS flow on real, manufacturable technology — and several Google-sponsored shuttle runs have taped out functional chips using SKY130 at zero cost.
What PDK means for AI chip teams. Designing a frontier AI accelerator at 3–5 nm means working with a PDK that contains: ~4800 standard cells × 5+ PVT corners (24,000+ Liberty views), 600-parameter FinFET/GAA SPICE models, 4000+ DRC rules, multi-patterning-aware coloring constraints, and EM limits that require coupled thermal-electrical analysis. The PDK is updated quarterly as the foundry improves the process; each update can shift timing margins by 5–10%, requiring re-validation of the entire design. The PDK is not documentation — it is the executable specification of the manufacturing process.
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