Layout design | ChipFoundryServices

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Layout design is the physical-design discipline of transforming a logical circuit netlist into geometric shapes on silicon — assigning every transistor, standard cell, wire, and via to precise coordinates on the chip die so the resulting pattern can be manufactured by the foundry's lithography, etch, and deposition equipment. It is where electrical intent becomes physical reality: the layout determines the actual area, speed, power, and yield of the chip. Every rectangle in a GDS file that goes to TSMC or Samsung was placed and routed by a layout design flow.

The digital layout flow — place and route. For digital designs (the bulk of an AI accelerator), layout is automated by EDA tools in a sequence called PnR (place-and-route):

Step	What happens	Key tool	Quality metric
Floorplanning	Assign chip area to major blocks (compute cores, memory, I/O ring, PLL)	Innovus, ICC2	Block aspect ratios, wire planning
Power planning	Design the VDD/VSS power grid (stripes, rings, via stacks)	Innovus, ICC2	IR-drop < 5% VDD at peak current
Placement	Position millions of standard cells in rows minimizing wirelength	Innovus, ICC2	Half-perimeter wirelength (HPWL)
Clock tree synthesis	Build balanced buffer tree from PLL to all flip-flops	CCOpt, CTS	Skew < 30 ps, insertion delay
Routing	Connect all cell pins through the metal stack (M1–M15)	NanoRoute, ICC2	Congestion, DRC-clean, timing
Optimization	Fix timing violations (resize cells, add buffers, reroute)	Innovus ECO, ICC2	Setup/hold slack ≥ 0 at all corners
Sign-off	DRC, LVS, STA, power, EM — all must pass clean	Calibre, PrimeTime	Zero violations

Analog and custom layout — the manual art. While digital layout is automated, analog/mixed-signal circuits (PLLs, ADCs, SerDes, voltage regulators, I/O pads) are laid out by hand or semi-custom. An analog layout engineer:

Matches devices by placing symmetric transistor pairs (common-centroid, interdigitated) to cancel process gradients that cause offset
Guards against noise with deep n-well isolation, substrate taps, and shielding
Minimizes parasitics by keeping critical signal paths short with wide, low-resistance routing
Follows DRC religiously while optimizing for electrical performance that automated tools can't capture

Analog layout is slow (weeks per block) and requires deep process knowledge — it's one of the most specialized and scarce skills in semiconductor design.

Physical design constraints — what the layout must satisfy:

Timing closure: every setup and hold path must have positive slack across all PVT corners after parasitic extraction
DRC clean: every polygon satisfies 3000–5000 foundry geometric rules (minimum width, spacing, enclosure, density)
LVS clean: extracted netlist matches the schematic — correct connectivity with no shorts or opens
EM clean: current density in every wire and via stays below the electromigration limit (see the CFS electromigration keyword)
IR-drop: voltage at every cell stays within 5% of nominal VDD under worst-case switching
Antenna clean: metal-to-gate-area ratios during etch stay within the plasma-damage threshold

Layout at advanced nodes — what changes below 7 nm:

Fin quantization (FinFET): transistor width is quantized to integer numbers of fins — you can't have 2.5 fins. Layout must use legal fin counts.
Multi-patterning (SADP/SAQP/EUV): some metal layers are split across 2–4 masks. Layout must satisfy coloring constraints — adjacent wires on the same mask must be farther apart.
Pin access: at sub-24 nm metal pitch, standard-cell pin access becomes extremely constrained. Only specific grid points on M1/M2 are legal connection points.
Backside power delivery (2 nm): power rails move to the wafer backside, freeing front-side routing tracks but adding new layout rules for nano-TSVs.

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Layout runtime and compute cost. Full-chip place-and-route of a modern GPU (50–100 million cell instances, 15 metal layers) runs for 2–7 days on a high-end server (128+ cores, 500+ GB RAM). Multiple iterations are needed as timing/DRC violations are found and fixed. Total PnR compute for a single tape-out can exceed 100,000 CPU-hours — making layout one of the most computationally expensive steps in chip design, rivaling only verification.

Layout and the CFS platform. The CFS Standard Cell keyword describes the building blocks that layout assembles; the DRC keyword covers the rules it must satisfy; the Clock Tree keyword covers CTS; the Interconnect Simulator at /interconnect models the wire RC delay that routing creates; and the Thermal Simulator at /thermal captures the hotspots that placement density causes.

layout designphysical designplace and route flowchip layoutic layoutcustom layoutpnr flow

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