Layout Versus Schematic verification confirms that the physical chip layout correctly implements the intended circuit schematic. LVS catches errors where the layout has wrong connections, missing devices, or extra parasitic elements that differ from the design intent.

What LVS Does

Step 1 - Layout Extraction: Extracts a netlist from the physical layout by recognizing devices (transistors, resistors, capacitors) and tracing their connections through metal/via layers. Step 2 - Schematic Netlist: The reference circuit netlist (from schematic capture or synthesis). Step 3 - Comparison: Compares the extracted layout netlist against the schematic netlist. Reports mismatches.

Common LVS Errors

Shorts: Two nets that should be separate are connected in layout. Opens: A net that should be continuous is broken (missing via, broken metal). Missing devices: Transistor not formed correctly in layout (wrong layer overlap). Parameter mismatch: Device exists but has wrong W/L (width/length) ratio. Extra devices: Parasitic transistors formed by unintended layer overlaps.

LVS Tools

• Siemens Calibre LVS: Industry standard, gold-reference for signoff • Synopsys IC Validator LVS: Integrated with Synopsys design flow • Cadence Pegasus LVS: Integrated with Cadence Virtuoso and digital flows

LVS Signoff

Clean LVS (0 errors) is mandatory for tape-out. For full-chip designs with billions of transistors, LVS runtime can be hours to days. Hierarchical LVS speeds up by verifying repeated blocks once and reusing results. LVS waivers are extremely rare—almost all errors must be resolved.