A leading-edge or advanced node refers to the latest and smallest process technology available from foundries at any given time. As of 2024-2025, this means 3nm and 2nm class technologies.

What "Node" Actually Means

Historically, the node name (e.g., 90nm, 45nm) referred to the physical gate length of the transistor. Today, node names like "3nm" are marketing labels—the actual minimum feature sizes are much larger. What matters is transistor density (millions of transistors per mm²) and performance/power improvements per generation.

Current Leading Edge (2024-2025)

• TSMC N3/N3E: 3nm FinFET. Used in Apple A17 Pro, M3 series • Samsung 3GAE/3GAP: 3nm GAA (nanosheet). First production GAA • Intel 18A: ~2nm equivalent with RibbonFET (nanosheet) and backside power delivery • TSMC N2: 2nm GAA nanosheet, targeted for 2025 production

Why Leading Edge Is Expensive

The cost of building a leading-edge fab exceeds $20 billion. A full mask set costs $5-10 million. Each technology generation requires EUV lithography ($350M per scanner), more complex process flows (1000+ steps), and years of R&D. Only three companies (TSMC, Samsung, Intel) can manufacture at leading edge.

Who Needs Leading Edge?

High-performance computing (CPUs, GPUs, AI accelerators) and mobile processors (smartphones). Most chips—automotive, industrial, IoT—use mature nodes (28nm and above) that are far cheaper and perfectly adequate.