Leakage Current — unwanted current that flows through transistors even when they are "off," consuming static power and creating a fundamental scaling challenge.

Types of Leakage

• Subthreshold Leakage: Current through the channel when $V_{gs} < V_{th}$. Exponentially depends on $V_{th}$: 10x increase for every ~100mV decrease in $V_{th}$
• Gate Leakage: Quantum tunneling through the thin gate oxide. Solved by high-k dielectrics (hafnium oxide replaced SiO2)
• Junction Leakage: Reverse-bias current through source/drain-to-body junctions
• GIDL (Gate-Induced Drain Leakage): Band-to-band tunneling at drain-gate overlap

Impact at Advanced Nodes

• At 7nm and below, leakage power can be 30–50% of total chip power
• A modern 5nm chip with billions of transistors: Leakage alone can be 10–50W
• This is why power gating (shutting off unused blocks) is essential

Mitigation

• Multi-$V_{th}$ libraries: Use HVT cells on non-critical paths
• Power gating: Cut VDD to idle blocks
• Body biasing: Raise $V_{th}$ dynamically when performance isn't needed
• FinFET/GAA: Better gate control reduces subthreshold leakage
• High-k gate dielectric: Eliminated gate leakage as a concern

Leakage current is the primary reason chip power hasn't scaled linearly with Moore's Law — managing it is a central challenge of modern semiconductor design.