LEF (Library Exchange Format) is an ASCII file format that describes the physical properties of standard cells and technology rules — providing the place-and-route tool with the information needed to place cells and route interconnects without requiring full cell layout.

Why LEF Exists

• Full GDS layout: Contains all transistors, contacts, every metal layer — too detailed for P&R.
• P&R tool only needs to know: Cell size, pin locations, obstruction areas, routing rules.
• LEF: Lightweight abstract representation → P&R tool runs 10x faster than with full GDS.

LEF File Types

Technology LEF (tech.lef):

• Describes metal layer stack, via definitions, design rules.
• Metal layer names (M1, M2 ... M15+), preferred routing direction.
• Minimum width, spacing, pitch for each layer.
• Via rules: Via size, enclosure, spacing.
• Antenna rules (metal area to gate area ratios).

Cell LEF (cells.lef):

• One entry per standard cell.
• MACRO statement: Cell name, size (width × height in units of site).
• PIN statement: Each pin name, direction (INPUT/OUTPUT), use (SIGNAL/POWER/CLOCK).
• PORT statement: Pin shape on which metal layer, exact coordinates.
• OBS statement: Obstruction layers — areas inside cell that the router cannot use.

Example LEF Snippet

MACRO INV_X1
  CLASS CORE ;
  ORIGIN 0.000 0.000 ;
  SIZE 0.48 BY 2.40 ;
  PIN A
    DIRECTION INPUT ;
    PORT LAYER M1 ;
      RECT 0.12 0.60 0.24 0.90 ;
    END
  END A
  PIN Z
    DIRECTION OUTPUT ;
    PORT LAYER M1 ;
      RECT 0.28 0.60 0.40 0.90 ;
    END
  END Z
END INV_X1

Relationship to GDS

• P&R uses LEF for placement and routing → produces DEF (Design Exchange Format).
• At tapeout: DEF + GDS merged → full chip GDS for mask making.
• LVS requires full GDS; P&R requires only LEF.

LEF is the physical interface between IP/standard cell libraries and the P&R tool — proper LEF characterization is essential for correct placement, DRC-clean routing, and accurate parasitic extraction in the sign-off flow.