Line width roughness is the statistical variation of the physical distance between opposing edges of a patterned line sampled along its longitudinal length, commonly quantified as three times the standard deviation ($3\sigma_{\text{LWR}}$) of measured critical dimensions. While line edge roughness (LER) measures the spatial deviation of a single isolated boundary, line width roughness captures the coupled variance of both edges ($w(y) = x_{\text{right}}(y) - x_{\text{left}}(y)$), directly governing transistor channel length variability, gate threshold voltage ($V_{\text{th}}$) dispersion, sub-threshold drain leakage ($I_{\text{off}}$), and interconnect resistance fluctuation. In sub-3nm nanosheet logic and dense memory arrays, LWR does not scale down proportionally with feature size, causing stochastic critical dimension variation to consume an increasingly severe fraction of the total error budget.

Line width roughness relates directly to single-edge roughness through the spatial cross-correlation between opposing line edges. If the position deviations of the left and right edges along coordinate $y$ are denoted $\delta x_L(y)$ and $\delta x_R(y)$, the total variance of the local feature width $w(y) = w_0 + \delta x_R(y) - \delta x_L(y)$ is derived as:

where $\rho_{LR}$ is the cross-edge correlation coefficient ($-1 \le \rho_{LR} \le 1$). In optical projection lithography near resolution limits and in EUV lithography where photon shot noise dominates, the two edges fluctuate independently ($\rho_{LR} \approx 0$). Consequently, line width roughness is fundamentally larger than single-edge roughness by a factor of $\sqrt{2}$:

Power spectral density (PSD) decomposition separates high-frequency noise from low-frequency CD bias. A single standard deviation value ($3\sigma_{\text{LWR}}$) provides an incomplete description because it fails to capture the spatial wavelength distribution of roughness. Calculating the Fourier transform of the line width autocorrelation function yields the power spectral density:

where $\text{PSD}(0)$ is the low-frequency roughness plateau, $\xi$ is the spatial correlation length (typically $10\text{--}30\text{ nm}$ in chemically amplified resists), $H$ is the Hurst roughness exponent ($0 < H \le 1$), and $f$ is spatial frequency ($1/\text{nm}$). High-frequency roughness ($f > 1/\xi$) smooths during subsequent plasma etching, whereas low-frequency roughness ($f < 1/\xi$) transfers directly into the silicon channel, causing severe transistor gate length mismatch.

LWR in transistor gate channels causes exponential amplification of off-state drain leakage current ($I_{\text{off}}$). Because sub-threshold leakage current scales exponentially with channel length ($I_{\text{off}} \propto \exp(-q V_{\text{th}} / k_B T) \propto \exp(-L_{\text{eff}} / l_{\text{char}})$), localized pinch points where line width narrows experience severe drain-induced barrier lowering (DIBL). As a result, the average leakage current across a rough gate is substantially higher than that of an ideal smooth gate of identical average CD:

where $l_{\text{char}}$ is the characteristic electrostatics scaling length of the device. In a 3nm nanosheet FET with $L_g = 12\text{ nm}$, an unmitigated $3\sigma_{\text{LWR}}$ of $2.5\text{ nm}$ can increase total static standby power by more than $300\%$.

Metrology measurement noise de-embedding is required to obtain unbiased physical line width roughness. When automated critical-dimension scanning electron microscopes (CD-SEM) scan a feature, primary electron beam Poisson shot noise adds high-frequency white noise to the measured edge position. Reporting the raw standard deviation overestimates physical wafer roughness. Rigorous metrology fits the high-frequency floor of the experimental PSD to extract and subtract SEM noise:

Post-lithography plasma smoothing and directional gas cluster ion beam (GCIB) etching mitigate high-frequency LWR. During plasma pattern transfer through the underlying bottom antireflective coating (BARC) and spin-on carbon (SOC) hardmask, pulsed hydrogen/methane or fluorocarbon chemistries preferentially sputter sharp roughness asperities. This chemical-mechanical ion bombardment suppresses high-frequency PSD components, reducing line width roughness by $20\text{--}35\%$ before the pattern reaches the active silicon channel.

st=>start: Acquire multi-frame high-resolution CD-SEM top-down images along line
edges=>operation: Extract left edge x_L(y) and right edge x_R(y) position profiles
lwr_calc=>operation: Compute local width w(y) = x_R(y) - x_L(y) and raw 3σ_LWR
psd=>operation: Perform Fast Fourier Transform (FFT) to extract Power Spectral Density PSD(f)
unbias=>operation: De-embed high-frequency CD-SEM white noise to extract σ_unbiased and ξ
spec=>condition: Unbiased 3σ_LWR ≤ 1.2nm and cross-edge correlation within limits?
smooth=>operation: Apply directional plasma post-treatment and optimize resist PEB chemistry
pass=>end: Qualified low-roughness pattern baseline ready for transistor gate etch
st->edges->lwr_calc->psd->unbias->spec
spec(yes)->pass
spec(no)->smooth->st

Ensuring nanometer-scale transistor matching requires treating line width roughness as a stochastic-photon-acid-diffusion-and-channel-leakage lens. As physical gate lengths scale toward single-digit nanometers, average critical dimension becomes an incomplete metric without full stochastic roughness characterization. Co-optimizing resist quantum efficiency, optical image log-slope, de-embedded PSD metrics, and plasma smoothing ensures that advanced logic chips deliver high operating frequencies without runaway parametric leakage.