Lithography Simulation is the computational modeling of the complete photolithographic patterning process — from mask design through aerial image formation, photoresist exposure kinetics, post-exposure bake (PEB) diffusion, and resist development — predicting the final printed pattern dimensions, edge placement error (EPE), process window, and the corrections needed (OPC, SMO, ILT) to ensure that nanometer-scale features on the photomask faithfully transfer to the silicon wafer despite diffraction and process variation.

What Is Lithography Simulation?

Lithography exposes a photoresist-coated wafer through a patterned mask using UV light. Below the diffraction limit of the optical system, the image formed on the wafer differs substantially from the mask pattern — simulation predicts and corrects for this:

Optical Image Formation (Aerial Image)

The aerial image intensity distribution on the wafer is computed using Hopkins' or Abbe's formulation of partial coherence imaging, incorporating:

• Illumination Source: Dipole, quadrupole, annular, free-form (SMO-optimized) — each produces characteristic diffraction patterns.
• Numerical Aperture (NA): Higher NA captures more diffracted orders and resolves finer features. Immersion lithography (NA = 1.35 for 193i) and EUV (NA = 0.33, 0.55 for High-NA EUV) have fundamentally different image formation physics.
• Mask Topology Effects (EMF/3D Mask): At EUV wavelengths (13.5 nm), mask features are comparable in scale to the wavelength. Rigorous electromagnetic simulations (FDTD, RCWA) must replace scalar diffraction models to accurately predict EUV mask shadowing and phase effects from absorber topology.

Resist Model

The photoresist response to the aerial image involves multiple physical and chemical processes:

• Exposure: Acid generation from photoacid generators (PAGs) proportional to absorbed dose.
• PEB Diffusion: Thermal diffusion of acid molecules during post-exposure bake smooths the latent image, limiting resolution — acid diffusion length (Lmin ~3–8 nm) defines the fundamental resist resolution limit.
• Development: Resist dissolution rate depends on local acid concentration through a contrast function. Development simulation predicts the 3D resist profile using string or level set methods.

Why Lithography Simulation Matters

• Optical Proximity Correction (OPC): Diffraction causes corners to round, line ends to pull back, and pitch-dependent CD variation. OPC pre-distorts the mask to compensate — today's OPC corrections are computed by iterative lithography simulation across billions of edge segments per reticle, with simulation-computed mask shapes that bear little resemblance to the desired wafer pattern.
• Mask Cost Avoidance: Advanced photomasks cost $5–15M per layer for EUV (full reticle). A single fatal OPC error discovered after mask fabrication results in total mask remake cost. Comprehensive simulation validation before mask tape-out is not optional — it is the primary cost control mechanism in advanced process development.
• Process Window Analysis: Manufacturing requires that features print correctly across focus and exposure dose variations (process window). Simulation generates focus-exposure matrices (FEM) to quantify the process window, identifying conditions where defects first form and guiding the scanner recipe for maximum yield.
• Stochastic Effects (EUV): EUV uses extremely low photon counts per feature — a 10 nm contact hole at typical EUV dose receives fewer than 15 photons. Photon shot noise causes stochastic variation in edge placement that cannot be predicted by deterministic models. Monte Carlo stochastic resist simulation quantifies the probability of line-edge roughness (LER), bridge defects, and hole closure.
• Source-Mask Optimization (SMO): Joint optimization of illumination source shape and mask pattern through simulation converges to illumination/mask combinations that maximize the process window for a target layout — a computation requiring millions of simulation evaluations.

Tools

• Synopsys Sentaurus Lithography (formerly Prolith): Industry-standard resist and aerial image simulation for 193i and EUV.
• ASML Tachyon / Brion: Advanced OPC and SMO computational lithography tools used in high-volume manufacturing.
• KLayout: Open-source layout viewer with lithography simulation plugins.

Lithography Simulation is predicting the shadow of light through a nanoscale lens — computationally modeling how photons diffract through nanometer-scale mask openings, interact with photochemical resist, and define the critical geometric patterns that determine whether a chip's transistors will switch correctly, powering the computational lithography industry that now shapes masks to bear little resemblance to their intended patterns in order to print those patterns correctly on silicon.