Lithography simulation is the computational twin of the patterning process: it predicts how a mask, illumination source, projection lens, resist stack, bake, and develop recipe will print on the wafer before the fab spends time on an actual split lot.

The simulator starts with the aerial image. Optical models estimate the intensity field that reaches the resist after diffraction through the mask and filtering by the projection optics. In compact form, a coherent imaging step treats the pupil as $P$ and the mask as $M$:

For production OPC, this expands into partial-coherence models, source-mask optimization, mask three-dimensional effects, aberrations, flare, and calibrated resist behavior. EUV adds more sensitivity to stochastic photon statistics and mask shadowing, so the model must be tied closely to metrology from real wafers.

The useful output is not a pretty image; it is a manufacturability prediction. Engineers look for edge placement error, critical-dimension error, process window, hot spots, and the dose-focus margin that keeps a pattern printable across the wafer and across lots.

The guardrail is calibration. A simulator that is mathematically elegant but not anchored to wafer data will miss the effects that decide yield. Good lithography simulation is therefore a loop: measure contours, fit the model, predict failures, correct the mask, and verify that edge placement error converges before tapeout.