Local Silicon Interconnect (LSI) is a small silicon bridge die embedded within an organic interposer or substrate that provides fine-pitch routing between adjacent chiplets — offering silicon-interposer-grade wiring density (0.4-2 μm line/space) only at the chiplet-to-chiplet interface where it is needed, while the rest of the package uses lower-cost organic routing, combining the performance of silicon interconnects with the cost and size advantages of organic substrates.
What Is LSI?
- Definition: A small silicon die (typically 5-50 mm²) containing 2-4 metal routing layers that is embedded in or bonded to an organic substrate at the boundary between two adjacent chiplets — providing the fine-pitch wiring needed for high-bandwidth die-to-die communication without requiring a full-size silicon interposer.
- TSMC CoWoS-L: LSI is the key technology in TSMC's CoWoS-L (CoWoS-Large) platform — multiple LSI bridges are embedded in an organic RDL interposer to connect chiplets, enabling package sizes much larger than what a single silicon interposer can support.
- Bridge Concept: LSI is functionally similar to Intel's EMIB (Embedded Multi-Die Interconnect Bridge) — both embed small silicon bridges in organic substrates to provide localized fine-pitch routing. The key difference is implementation: EMIB is embedded in the package substrate, while LSI is embedded in an organic interposer layer.
- Selective Silicon: The insight behind LSI is that fine-pitch silicon routing is only needed at chiplet boundaries (where die-to-die signals cross) — the rest of the interposer area handles power distribution and coarse routing that organic substrates can support adequately.
Why LSI Matters
- Scalability Beyond CoWoS-S: TSMC's CoWoS-S silicon interposer is limited to ~2500 mm² (stitched) — CoWoS-L with LSI bridges can support interposer areas of 3000-5000+ mm², enabling next-generation AI GPUs with more chiplets and more HBM stacks.
- Cost Reduction: A full silicon interposer for a large AI GPU costs thousands of dollars — replacing 80-90% of the silicon area with organic substrate while keeping silicon bridges only at chiplet interfaces reduces interposer cost by 40-60%.
- NVIDIA Blackwell: NVIDIA's B200/B300 GPUs are expected to use CoWoS-L with LSI bridges — the two-die GPU configuration with 8 HBM stacks requires a package area that exceeds practical CoWoS-S silicon interposer limits.
- Capacity Relief: Silicon interposer capacity at TSMC is severely constrained by AI GPU demand — CoWoS-L with LSI uses much less silicon area per package, effectively multiplying TSMC's advanced packaging capacity.
LSI Technical Details
- Bridge Size: Typically 3-10 mm wide × 5-15 mm long — just large enough to span the gap between adjacent chiplets with sufficient routing channels.
- Metal Layers: 2-4 copper metal layers with 0.4-2 μm line/space — same lithographic quality as a full silicon interposer.
- Bump Interface: Top-side micro-bumps at 40-55 μm pitch connect to the chiplets above — bottom-side connections bond to the organic interposer RDL.
- Embedding: LSI bridges are placed face-down in cavities in the organic interposer and encapsulated — the organic RDL layers are then built up over the bridges.
| Feature | CoWoS-S (Full Si) | CoWoS-L (LSI + Organic) | EMIB |
|---------|-------------------|------------------------|------|
| Fine-Pitch Area | Entire interposer | Bridge regions only | Bridge regions only |
| Min L/S | 0.4 μm | 0.4 μm (bridge) | 2 μm |
| Max Package Size | ~2500 mm² | 3000-5000+ mm² | Limited by substrate |
| Cost | High | Medium | Medium |
| TSVs | Full interposer | Bridge only | Bridge only |
| Organic Area | None | 80-90% | 100% (substrate) |
| Key Product | NVIDIA H100 | NVIDIA B200 | Intel Ponte Vecchio |
LSI is the bridge technology enabling the next generation of AI GPU packaging — providing silicon-quality interconnect density at chiplet boundaries while leveraging organic substrates for the remaining package area, achieving the larger package sizes and lower costs needed for multi-die AI accelerators that exceed the practical limits of full silicon interposers.