Logic synthesis is the step that turns a chip's register-transfer-level (RTL) description into a gate-level netlist — a concrete network of logic gates and flip-flops drawn from a specific manufacturing library. It is the compiler of the hardware world: an engineer writes behavior in Verilog or VHDL, and the synthesis tool translates and optimizes it into real cells while honoring timing, area, and power goals. Tools like Synopsys Design Compiler/Fusion, Cadence Genus, and the open-source Yosys perform this translation, producing the netlist that place-and-route later gives physical form.\n\nIt reads three inputs: the RTL, a cell library, and constraints. The RTL says what the circuit should do. The standard-cell library (a .lib/Liberty file) lists the gates the foundry offers — each AND, OR, multiplexer, and flip-flop with its delay, area, and power characterized at various drive strengths and threshold-voltage flavors. The constraints (an SDC file) state the target clock period, input and output timing, and other requirements. Synthesis exists to find a netlist, built only from library cells, that implements the RTL and meets those constraints — and there are astronomically many such netlists, which is why optimization is the heart of the tool.\n\nIt optimizes twice: technology-independent, then technology mapping. First the tool elaborates the RTL into a generic Boolean representation and simplifies it — sharing common sub-expressions, removing redundant logic, restructuring equations — without yet committing to specific gates. Then technology mapping selects actual library cells to cover that logic, choosing drive strengths and cell variants, and restructures timing-critical paths to hit the clock (buffering, cloning, re-timing). Throughout, the tool trades power, performance, and area: a tighter clock constraint pushes it to spend more area and power on faster cells, while a relaxed one lets it shrink and save energy. The result is verified logically equivalent to the RTL by formal equivalence checking.\n\n| | Input / stage | Role |\n|---|---|---|\n| RTL | Verilog / VHDL | the behavior to implement |\n| .lib (Liberty) | standard-cell library | available gates + their PPA |\n| SDC | constraints | clock, I/O timing goals |\n| Elaborate + optimize | tech-independent | simplify Boolean logic |\n| Technology map | tech-dependent | pick real cells, fix timing |\n| Output | gate-level netlist | cells + flip-flops + wires |\n\n``svg\n\n``\n\nSynthesis is where the design's speed, size, and power are largely decided. Because it chooses how logic is structured and which cells implement it, synthesis sets the first real estimate of whether the design will meet timing and how big it will be — the numbers place-and-route then refines with physical reality. Modern physical-synthesis tools even fold in early placement so their timing estimates account for wire delay, since at advanced nodes interconnect dominates. Getting constraints right matters enormously: under-constrain and the netlist is slower than it needs to be, over-constrain and the tool bloats area and power chasing a clock the design does not require. Synthesis output feeds directly into static timing analysis and place-and-route.\n\nRead logic synthesis through a quant lens rather than a 'compile the code' lens: the tool is a search over netlists minimizing area and power subject to a hard timing constraint, and the clock period in the SDC is the dial that moves the whole result. Loosen it and synthesis returns a smaller, cooler netlist; tighten it and the tool spends gates, drive strength, and leakage to buy delay on the critical path, until no restructuring can close the gap and you must change the RTL or pipeline it. Everything downstream inherits this trade, so the quality of a chip is set less by writing more RTL than by how aggressively its register-to-register paths are constrained here.