Low-Power Design with UPF/CPF is the systematic design methodology that reduces both dynamic and static power consumption through architectural techniques (power gating, voltage scaling, clock gating, multi-Vt selection) specified using the UPF (Unified Power Format) standard — enabling modern mobile SoCs to achieve 1-2 day battery life despite containing billions of transistors, by selectively shutting down, voltage-scaling, or clock-gating unused blocks.

Power Components

• Dynamic Power: P_dyn = α × C × V² × f (α = switching activity, C = load capacitance, V = supply voltage, f = frequency). Reduced by lowering voltage, frequency, or switching activity.
• Static (Leakage) Power: P_leak = I_leak × V. Exponentially sensitive to Vth and temperature. At 5nm, leakage constitutes 30-50% of total power. Reduced by power gating (cutting supply) or using high-Vt cells.

Low-Power Techniques

• Clock Gating: Disable the clock to flip-flops whose data is not changing. Reduces dynamic power by 30-60% with minimal area overhead. Automatically inserted by synthesis tools based on enable signal analysis.
• Multi-Voltage Domains (DVFS): Different blocks operate at different supply voltages — performance-critical blocks at high voltage, non-critical blocks at reduced voltage. Dynamic Voltage-Frequency Scaling (DVFS) adjusts voltage and frequency at runtime based on workload demand. Level shifters convert signals crossing voltage domain boundaries.
• Power Gating: Completely disconnect the supply to idle blocks using header (PMOS) or footer (NMOS) power switches. Eliminates both dynamic and leakage power in gated domains. Requires:
• Isolation cells: Clamp outputs of powered-off domains to known values to prevent floating inputs on powered-on logic.
• Retention flip-flops: Special flip-flops with a secondary always-on supply that preserves state during power-off. When the domain powers up, the retained state is restored in one cycle.
• Power-on sequence: Controlled ramp-up of the header switches to limit inrush current (rush current can cause voltage droop on the always-on supply).

UPF (Unified Power Format)

The IEEE 1801 standard for specifying power intent:

• create_power_domain: Defines which logic blocks belong to which power domain.
• create_supply_set: Specifies VDD/VSS supplies and their voltage levels.
• set_isolation: Specifies isolation strategy for domain outputs.
• set_retention: Specifies which flip-flops in a gatable domain are retention type.
• add_power_state_table: Defines legal power states (on, off, standby) and transitions.

The UPF file is consumed by synthesis, PnR, and verification tools to implement, place, and verify all power management structures.

Low-Power Design is the discipline that makes portable computing possible — transforming billion-transistor SoCs from power-hungry furnaces into energy-sipping marvels that run all day on a battery the size of a credit card.