Power-Aware Simulation and UPF Verification is the specialized verification methodology that simulates the behavior of a chip design with its power management architecture (power gating, voltage scaling, retention) actively modeled — verifying that isolation cells correctly clamp outputs when a domain is powered off, retention registers properly save and restore state across power cycles, and level shifters correctly translate signals between voltage domains, catching power-related bugs that standard functional simulation completely misses.

Why Power-Aware Simulation

• Standard simulation: All signals are either 0 or 1 → power domains always assumed ON.
• Reality: Blocks power-gate (shut off) → outputs become undefined (X) → must be isolated.
• Without power simulation: Cannot verify isolation cells, retention, power sequencing.
• Power bugs: #1 cause of silicon failure in SoC designs with complex power management.

UPF (Unified Power Format)

# Define power domains
create_power_domain PD_CORE -elements {u_cpu_core}
create_power_domain PD_GPU  -elements {u_gpu} -shutoff_condition {!gpu_pwr_en}
create_power_domain PD_ALWAYS_ON -elements {u_pmu u_wakeup}

# Define power states
add_power_state PD_GPU -state ON  {-supply_expr {power == FULL_ON}}
add_power_state PD_GPU -state OFF {-supply_expr {power == OFF}}

# Isolation
set_isolation iso_gpu -domain PD_GPU \
    -isolation_power_net VDD_AON \
    -clamp_value 0 \
    -applies_to outputs

# Retention
set_retention ret_gpu -domain PD_GPU \
    -save_signal {gpu_save posedge} \
    -restore_signal {gpu_restore posedge}

What Power-Aware Simulation Checks

X-Propagation in Power Simulation

<svg viewBox="0 0 519 188" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="519" height="188" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9"> Domain A (ON)      Domain B (OFF)</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">┌─────────┐</tspan><tspan fill="#c9d1d9">        </tspan><tspan fill="#6e7681">┌─────────┐</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Logic   </tspan><tspan fill="#6e7681">│─</tspan><tspan fill="#c9d1d9">signal</tspan><tspan fill="#6e7681">─│</tspan><tspan fill="#c9d1d9"> X X X X </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9">  </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> All signals in B are X</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> working </tspan><tspan fill="#6e7681">│←─────┤</tspan><tspan fill="#c9d1d9"> X X X X </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">└─────────┘</tspan><tspan fill="#c9d1d9">  </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">└─────────┘</tspan></text><text xml:space="preserve" x="20" y="126.7"><tspan fill="#c9d1d9">          [ISO cell]</tspan></text><text xml:space="preserve" x="20" y="145.7"><tspan fill="#c9d1d9">          clamps B output to 0</tspan></text><text xml:space="preserve" x="20" y="164.7"><tspan fill="#c9d1d9">          </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> A sees 0, not X </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> correct behavior</tspan></text></g></svg>

• Without isolation: A receives X from B → X propagates through A → false failures OR masked real bugs.
• Correct isolation: A receives clamped value (0 or 1) → design functions correctly.

Power-Aware Simulation Flow

1. Read RTL + UPF (power intent). 2. Simulator creates supply network model (power switches, isolation cells, retention cells). 3. Run testbench with power state transitions:

• Power on GPU → run workload → save state → power off GPU → verify isolation.
• Power on GPU → restore state → verify data integrity.

4. Check for:

• No X propagation to active domains.
• Correct isolation values.
• State retention across power cycles.
• Correct power-on reset behavior.

Common Power Bugs Found

Verification Completeness

• Formal UPF verification: Statically checks all domain crossings have isolation/level shifters.
• Simulation: Dynamically verifies behavior during power transitions.
• Both needed: Formal catches structural issues, simulation catches sequencing bugs.

Power-aware simulation is the verification methodology that prevents the most expensive class of silicon bugs in modern SoCs — with power management involving dozens of power domains, hundreds of isolation cells, and complex power sequencing protocols, the failure to properly verify power intent through UPF-driven simulation is the leading cause of first-silicon failures in complex SoC designs, making power-aware verification a non-negotiable requirement for tapeout signoff.