Machine Model (MM) ESD Test is a legacy electrostatic discharge (ESD) test methodology that simulates the discharge of a charged metallic object — such as a machine tool, fixture, or handling equipment — coming into contact with a device pin, characterized by an oscillatory waveform from a 200 pF capacitor discharged through near-zero resistance. Although officially deprecated by JEDEC in 2012 in favor of the Charged Device Model (CDM), the Machine Model remains relevant for legacy specifications, historical context, and understanding the ESD robustness requirements of devices manufactured through the 1990s and 2000s.
ESD Test Models: The Big Three
Semiconductor ESD testing uses three standardized models, each simulating a different real-world discharge scenario:
| Model | Abbreviation | Simulates | Circuit Model | Typical Range | Status |
|-------|-------------|-----------|--------------|---------------|--------|
| Human Body Model | HBM | Human touching a pin | 100 pF + 1.5 kΩ | ±500V to ±8kV | Active (ANSI/ESDA/JEDEC JS-001) |
| Machine Model | MM | Metal tool/machine | 200 pF + ~0Ω | ±100V to ±400V | Deprecated (2012) |
| Charged Device Model | CDM | Device itself discharges | Device capacitance | ±125V to ±2kV | Active (ANSI/ESDA/JEDEC JS-002) |
Machine Model Circuit and Waveform
The MM test circuit consists of:
- Capacitor: $C = 200$ pF (charged to test voltage)
- Series resistance: $R \approx 0 \Omega$ (only parasitic inductance $L \approx 0.75\ \mu H$)
- Standard: JESD22-A115
This LC circuit creates an oscillatory (ringing) waveform:
- Rise time: ~5-15 ns (much faster than HBM's 10 ns rise, 150 ns decay)
- Peak current: $I_{peak} = V_{test} \sqrt{C/L} \approx 3-8$ A for 100-400V test voltages
- Oscillation frequency: $f = 1/(2\pi\sqrt{LC}) \approx 14$ MHz
- Significantly more stressing than HBM at the same voltage due to faster rise time and higher peak current
Classification Levels (JESD22-A115)
| Class | Voltage | Protection Requirement |
|-------|---------|------------------------|
| Class A | ±100V | Lowest protection level |
| Class B | ±200V | Standard requirement in older specs |
| Class C | ±400V | High protection |
Why MM Was Deprecated
JEDEC retired the Machine Model in 2012 (JEDEC JESD469) for several reasons:
1. CDM better models real machine damage: In modern automated assembly, the dominant damage mechanism is a charged device discharging — not a charged machine discharging into a grounded device. CDM captures this more accurately.
2. Inconsistent results: MM waveforms are highly sensitive to the parasitic inductance of test fixtures, causing dramatically different results across different labs — making MM data unreliable for cross-company comparison
3. Duplicate coverage: Devices with adequate HBM and CDM protection were already well-protected against machine-type discharges. MM added no new information about real-world failure modes.
4. Industry consensus: The ESD Association (ESDA) and JEDEC jointly concluded MM testing should be discontinued.
Legacy Impact and Current Relevance
Despite deprecation, MM remains relevant for:
- Legacy customer specifications: Automotive customers (Tier 1 suppliers, OEMs) may still specify MM ratings in design requirements inherited from 1990s-2000s procurement standards. These specifications require compatibility testing even if the standard is deprecated.
- Historical data interpretation: MM ratings appear extensively in datasheets from the 1990s-2010s era. Understanding MM levels is needed to interpret old characterization data.
- Japanese industry standards: MM originated from Japanese semiconductor industry practices and remains in some Japan-specific standards longer than their Western counterparts.
- Legacy defense and space specifications: Long-lived defense programs may reference MM in their electronics specifications without updating to reflect industry changes.
Replacing MM with CDM
CDM is the current standard for machine-level discharge testing:
- Models the device itself charging up (from friction, contact with insulators) and then discharging through a pin
- This is the dominant failure mode in automated PCB assembly and handling
- CDM is particularly important for fine-pitch, large-die devices which accumulate more charge
- JEDEC JS-002 defines CDM classification: C1 (≤125V), C2 (125-250V), C3 (250-500V), C4 (≥500V)
ESD Design Protection at Device Level
ESD protection circuits in chips must withstand all applicable test models:
- HBM protection: Input/output diodes to power rails (ESD clamps), 100-200Ω series resistance
- CDM protection: Very low-resistance, fast-response clamps; on-die decoupling capacitors help
- MM (legacy): Oscillatory stress requires protection against both the forward and reverse polarity phases
- TLP (Transmission Line Pulse): Lab characterization tool — not a field standard, but used to design protection circuits with precise I-V characterization of ESD clamps
Understanding ESD test models — including deprecated ones like MM — is essential for semiconductor reliability engineers, package designers, and EDA engineers working on ESD protection circuit design.