SRAM Compiler — a tool that automatically generates custom SRAM memory blocks with specified dimensions, port configurations, and timing characteristics.

Why Compilers?

• Every chip needs memory (caches, buffers, register files)
• SRAM layout is highly regular but must be tuned for each size and port count
• Manual design for every needed configuration is impractical
• Compiler generates layout, netlist, timing models, and verification views in minutes

Configuration Parameters

• Word count (depth): 64, 128, 256, 512, 1024...
• Word width (bits): 8, 16, 32, 64, 128...
• Number of ports: 1RW, 1R1W, 2RW (trade-off: access bandwidth vs area)
• Mux factor: Column MUX ratio (affects aspect ratio)
• Voltage and timing corners

Generated Outputs

• GDSII layout (physical design)
• Liberty .lib (timing/power characterization)
• Verilog behavioral model (simulation)
• LEF (abstract layout for PnR)
• DRC/LVS clean guaranteed

SRAM in Modern Chips

• Apple M4: ~40% of die area is SRAM
• GPU register files, L1/L2 caches, buffers everywhere
• SRAM bit cell: 6T (standard), 8T (read-disturb free), custom (high-density)

SRAM compilers are among the most valuable IP deliverables from a foundry process development kit (PDK).