Memory Consistency Models are the formal specifications that define the legal orderings of memory operations (loads and stores) as observed by different processors in a shared-memory multiprocessor — determining when a store by one processor becomes visible to loads by other processors, where the choice of consistency model (sequential consistency, TSO, relaxed) fundamentally affects both the correctness of parallel programs and the hardware optimizations that processors can perform to improve performance.

Why Memory Consistency Is Non-Obvious

In a single-threaded program, loads and stores appear to execute in program order. In a multiprocessor, hardware optimizations (store buffers, out-of-order execution, write coalescing, cache coherence delays) can reorder when stores become visible to other processors. Without a consistency model, programmers cannot reason about the behavior of concurrent code.

Sequential Consistency (SC)

The strongest (most intuitive) model (Lamport, 1979): the result of any parallel execution is the same as if all operations were executed in SOME sequential order, and the operations of each individual processor appear in this sequence in program order. No reordering is allowed — stores by processor P are immediately visible to all other processors in program order.

SC precludes most hardware optimizations — processors cannot use store buffers, reorder loads past stores, or speculatively execute loads. No modern high-performance processor implements strict SC.

Total Store Order (TSO)

Used by x86 (Intel, AMD): stores may be delayed in a store buffer (other processors don't see them immediately), but stores from each processor appear in program order. Loads may bypass earlier stores to different addresses (store-load reordering is allowed); all other orderings are preserved.

Practically: x86 programmers rarely need explicit fences because TSO provides strong ordering. The main exception: store-load ordering requires MFENCE (or lock-prefixed instruction) for patterns like Dekker's algorithm or lock-free data structures.

Relaxed Consistency (ARM, RISC-V, POWER)

ARM and RISC-V allow all four reorderings: load-load, load-store, store-load, and store-store. Stores from one processor may become visible to different processors in different orders. This maximal relaxation enables aggressive hardware optimizations (out-of-order commit, write coalescing, independent memory banks) that improve single-thread performance.

Memory Barriers (Fences)

Programmers restore ordering where needed using fence instructions:

• DMB (ARM) / fence (RISC-V): Full memory barrier — all operations before the fence are visible to all processors before operations after the fence.
• Acquire: No load/store after the acquire can be reordered before it. Used when entering a critical section (locking).
• Release: No load/store before the release can be reordered after it. Used when leaving a critical section (unlocking).
• C++ Memory Order: std::memory_order_relaxed, _acquire, _release, _acq_rel, _seq_cst map to appropriate hardware fences on each architecture.

Impact on Software

Memory Consistency Models are the contract between hardware and software that defines the rules of concurrent memory access — the formal specification without which lock-free algorithms, concurrent data structures, and multi-threaded programs could not be written correctly across different processor architectures.