MEMS Process Integration CMOS is a hybrid manufacturing approach co-fabricating microelectromechanical systems alongside CMOS electronics on single die, enabling sensor/actuator integration with signal conditioning — reducing system cost and power consumption through monolithic implementation.

Monolithic Integration Challenges

MEMS mechanical structures (cantilevers, membranes) require specific processing: polysilicon deposition, sacrificial material removal, and mechanical release. Integrating MEMS with CMOS electronics complicates process flow: CMOS thermal budget (annealing steps reaching 900-1000°C) must not degrade MEMS structures or interconnect; MEMS requires different mask patterns and etch recipes than transistors. Solution: MEMS processing performed last — after all CMOS is complete, MEMS layers deposited and etched using dedicated processing. This monolithic integration enables: same die cost as pure CMOS (no assembly required), tight integration of mechanical and electrical signals, and system-level performance optimization.

Polysilicon Mechanical Layer

• Deposition: Low-pressure chemical vapor deposition (LPCVD) polysilicon deposited at 600-650°C from silane (SiH₄) precursor; thickness 1-5 μm typical for cantilevers and suspended structures
• Crystallinity: Polysilicon microstructure (grain size, orientation) affects mechanical properties; fine-grained polysilicon exhibits lower stiffness and higher damping than single-crystal silicon
• Stress Control: Intrinsic stress (compressive or tensile) during deposition affects mechanical resonance; stress compensation through multiple deposition runs (alternating tension/compression layers) enables stress-free structures
• Doping: In-situ phosphorus or boron doping during CVD enables electrical connection to CMOS electronics; doping concentration ~10¹⁹ cm⁻³ provides adequate conductivity

Sacrificial Layer Technology

• Material Selection: Silicon dioxide (SiO₂) most common sacrificial layer — easily removed via hydrofluoric acid without attacking polysilicon mechanical structures
• Deposition: LPCVD oxide or tetraethyl orthosilicate (TEOS) oxide via plasma-enhanced CVD; thickness determines suspension height (mechanical air-gap)
• Release Etch: Dilute HF (typically 10:1 HF:H₂O) selectively removes oxide at controlled rate (~400 nm/min); release time estimated from sacrificial layer thickness
• Stiction Mitigation: During sacrificial layer removal, capillary forces between suspended structure and substrate can cause mechanical sticking (stiction). Prevention: polymer coatings reducing friction, or critical-point drying removing liquid without capillary forces

Eutectic Bonding for MEMS Capping

• Bond Integrity: Many MEMS devices require hermetic enclosure preventing moisture and contamination ingress. Eutectic bonding employs metal-semiconductor mixture with lower melting point than pure components: Au-Si eutectic melts at 363°C (versus Au 1064°C, Si 1414°C)
• Bonding Process: Gold layer (2-5 μm) deposited on wafer surface; silicon cap (test mass or cover wafer) with complementary gold layer placed in contact; heating to 363-380°C melts gold enabling flow and bonding
• Joint Strength: Eutectic bond provides excellent mechanical strength and hermetic sealing; thermal cycling to -40°C/+85°C creates negligible stress due to similar thermal expansion coefficient (Au-Si composite matches silicon)
• Thermal Budget: Eutectic bonding temperature (363°C) well below typical CMOS metal reflow (260°C), enabling post-CMOS processing without damaging existing electronics

Integrated Transduction and Readout

• Capacitive Sensing: Suspended mechanical structure varies capacitance as it deflects; CMOS charge amplifier detects capacitance change with resolution <0.1 fF (femtofarad)
• Piezoresistive Sensing: Alternative employs resistance change in polysilicon under stress; piezoresistivity enables large signal change (resistance varies proportional to strain)
• Piezoelectric Integration: Emerging MEMS approaches incorporate piezoelectric thin films (AlN, PZT) enabling direct transduction without requiring separate sensing elements

MEMS Foundry Services

• Process Libraries: MEMS foundries (TSMC, X-Fab, other specialists) offer standardized MEMS process modules integrating with CMOS: cantilever beams (1-10 μm width), suspended membranes (10-100 μm diameter), and resonating structures
• Design Kits: MEMS foundries provide design kits including FEM (finite element method) simulations for mechanical response, electrical equivalent circuits, and layout design rules
• Multi-Project Wafers (MPW): Reduces NRE cost enabling startups to prototype MEMS concepts; mask costs amortized across multiple designers

Challenges and Advanced Integration

• Stress Management: Thermal cycling during CMOS processing creates stress migration affecting mechanical properties; stress compensation during film deposition essential
• Mechanical Q-Factor: Air damping in integrated MEMS limits quality factor (Q) to 100-1000 in atmospheric pressure; vacuum encapsulation achieves Q >10000 but requires specialized packaging
• Frequency Trim Capability: Post-fabrication frequency tuning (through electrostatic force) enables yield recovery for resonating MEMS even if mechanical parameters vary

Closing Summary

MEMS-CMOS monolithic integration represents a cost-effective paradigm enabling co-fabrication of mechanical sensors with signal conditioning electronics, leveraging polysilicon mechanical structures and sacrificial release etch — transforming sensor economics through single-die integration of transduction and amplification functions.