Metal Gate CMP is the polishing and planarization of the metal gate stack (W/TiN/HfO₂) in gate-last replacement metal gate (RMG) process — removing excess metal and dielectric to expose gate tops at a precise height — enabling high-performance, low-threshold-voltage matching gate stacks essential for sub-7 nm CMOS. Metal gate CMP is a critical enabler of advanced logic.
RMG Process Flow
In gate-last RMG, a sacrificial polysilicon gate is deposited and patterned first, then removed just before metal gate integration. This enables: (1) compatibility with raised S/D epitaxy (higher temperature), (2) independent metal gate process from gate patterning, and (3) flexibility in metal gate materials. After metal gate deposition (PVD TiN or ALD), the stack is overburden (excess metal/TiN on dielectric), and CMP planarizes to expose gate tops at a precise height (within a few nm of the top of the dielectric).
Tungsten Polishing Challenges
Tungsten has hardness ~8-9 (on Mohs scale), approaching abrasive particles (SiO₂ ~9). W CMP requires hard pads and aggressive slurries (SiO₂ 20-50 nm particles + oxidizing agents). Polishing rate is slow (~50-150 nm/min) and difficult to control. The W/TiN/HfO₂ stack requires selective polishing: high removal rate of W, low removal rate of HfO₂ (underlying dielectric). Selectivity of W:HfO₂ is typically 2:1 to 5:1, meaning HfO₂ is also polished (though slower).
Dishing and Erosion in Dense Arrays
CMP causes two main defects: (1) dishing — overpolishing of W within the gate (W sinks below surrounding dielectric), and (2) erosion — underpolishing of dielectric in sparse regions (W and dielectric remain proud of target). Dishing increases gate resistance and can cause shorts if severe. Erosion increases dielectric thickness and reduces capacitance. Both are exacerbated by pattern density variation: dense gate arrays are polished faster than sparse regions, leading to erosion in sparse areas.
CMP Endpoint Detection
Endpoint detection (EPD) is critical: when should polishing stop? Optical endpoint uses reflectance — the color changes when W is exposed through the transparent dielectric. However, optical EPD is confused by pattern density variation (dense areas reflect differently than sparse). Motor current increase also signals endpoint (increased friction when w is exposed). Modern tools use multi-EPD: optical + motor current + time-based to improve accuracy. Target accuracy is ±10-20 nm.
CMP Slurry Chemistry
Metal gate CMP slurries combine: (1) abrasive particles (SiO₂, Al₂O₃, CeO₂), (2) oxidizing agents (H₂O₂, KIO₄), (3) corrosion inhibitors (pH buffers, surfactants), and (4) binders. For W polishing, higher H₂O₂ concentration oxidizes W to WO₃ (higher removal rate) but risks dielectric over-polishing. For HfO₂ protection, pH and inhibitor chemistry must be tuned to slow HfO₂ removal. Selective slurries exist: "W-favoring" slurries accelerate W removal vs HfO₂. Post-CMP cleaning removes residual W particles and slurry residue.
Post-CMP Cleaning and Defect Mitigation
After CMP, SC1 (0.1 M NH₄OH + H₂O₂) removes organic residues and oxide particles; SC2 (0.1 M HCl + H₂O₂) removes metal contamination (Fe, Cu, W); dilute HF dip removes oxide residue. Incomplete cleaning leaves W particles (cause bridging shorts), metal contamination (increase leakage), or oxide residue (increase capacitance). Post-CMP inspection via electron microscopy detects dishing, erosion, and particle residues.
Metal Gate Uniformity and Vt Matching
Gate height variation directly impacts device threshold voltage (Vt): taller gates (less overpolish) have lower Vt (more effective oxide thickness). Across-die Vt variation of >50 mV is unacceptable for analog circuits. Metal gate CMP must achieve <±20 nm gate height uniformity across die. This requires: (1) careful CMP pad conditioning, (2) slurry chemistry optimization, (3) endpoint detection calibration, and (4) pattern density compensation (adding dummy features in sparse regions).
Gate Height and Capacitance Control
The height of the gate stack affects capacitance and performance. Taller gates (less effective oxide thickness) have slightly higher gate capacitance and lower Vt. However, excessive gate height increases gate resistance and delays. Typical gate height is controlled to within ±5% of target (~40-60 nm depending on node). Gate height measurement uses cross-section SEM or X-ray fluorescence.
Damage and Interface Degradation
CMP mechanical action (abrasive particles, pad friction) can damage the HfO₂/metal interface or introduce particle contamination. Organic residues from CMP slurry can degrade gate oxide reliability if not completely removed. Post-CMP defect inspection and cleaning protocols are critical.
Summary
Metal gate CMP is a highly engineered process, balancing aggressive W removal with protection of underlying HfO₂ and dielectric. Continued advances in slurry chemistry, endpoint detection, and pad technology are essential for gate-last RMG integration at advanced nodes.