Wafer Bumping is the back-end-of-line packaging process that deposits metallic interconnect bumps on the active surface of a semiconductor die — enabling flip-chip attachment where the die is mounted face-down onto a substrate or interposer with electrical connections formed through these bumps rather than traditional wire bonds, supporting higher I/O density, shorter interconnect lengths, and better thermal and electrical performance that modern high-performance chips demand.

Why Bumping Replaced Wire Bonding

Wire bonding connects die pads (at the chip perimeter) to substrate pads via thin gold or copper wires. Limitations: I/O count limited by perimeter length, long interconnect paths with high inductance, and the die must be mounted face-up (heat dissipated through the die back, not the shorter path through the substrate). Flip-chip bumping uses the entire die surface for I/O, supports thousands of connections in an area array, and provides shorter electrical paths.

Bump Types

• Solder Bumps (C4): Controlled Collapse Chip Connection — the original flip-chip technology (IBM, 1960s). Lead-free SnAg solder balls deposited on UBM (Under Bump Metallurgy). Pitch: 100-250 μm. Used for standard flip-chip packaging.
• Copper Pillar Bumps: Electroplated copper pillars (~40-80 μm height) with a thin solder cap for bonding. Superior electromigration resistance, better current carrying capacity, and finer pitch (40-80 μm) than solder bumps. Dominant technology for advanced packaging.
• Micro Bumps: Very small bumps (10-25 μm pitch) used for die-to-die connections in 2.5D (on interposer) and 3D (die stacking) configurations. Cu/Sn or Cu/Ni/Sn metallurgy. Essential for HBM memory stacking and chiplet architectures.
• Hybrid Bonding (Cu-Cu Direct): No solder at all — direct copper-to-copper bonding at sub-10 μm pitch. Used in advanced 3D stacking (AMD 3D V-Cache, TSMC SoIC). Achieves 10,000+ connections per mm² versus 400 for micro bumps.

Bumping Process Flow

1. UBM Deposition: Sputter adhesion layer (Ti/TiW), barrier layer (Ni/Cr), and wetting/solderable layer (Cu/Au) onto the die pad. 2. Photoresist Patterning: Define bump locations using thick photoresist (25-100 μm). 3. Electroplating: Plate Cu pillar and solder cap into the resist openings. 4. Resist Strip and UBM Etch: Remove photoresist and etch exposed UBM between bumps. 5. Reflow: Melt the solder cap to form a rounded profile for reliable bonding.

Bump Pitch Scaling Challenges

As pitch shrinks below 40 μm: solder bridging risk increases, underfill flow becomes difficult, thermal-mechanical stress per bump increases (fewer bumps sharing the load), and alignment tolerance tightens. Below 10 μm pitch, hybrid bonding replaces bumps entirely because solder-based approaches cannot achieve the required alignment and planarity.

Wafer Bumping is the metallurgical bridge between the nanometer world of transistors and the micrometer world of packages — each bump carrying power, ground, or signal at densities that wire bonding could never achieve, enabling the flip-chip and chiplet architectures that define modern processor packaging.