Micro-LED fabrication grows red, green, and blue emitters as compound-semiconductor epitaxial stacks, etches each emitter down to an isolated mesa only a few micrometers across, and then transfers hundreds of thousands to millions of those mesas onto a display backplane in a single mass-transfer step. Every stage compounds against the last: an epitaxial defect that a large LED tolerates becomes a catastrophic efficiency loss once the mesa shrinks to display-pixel size, and a transfer process that works at a 0.1% defect rate for a thousand pixels can still leave visible dead pixels once pixel count reaches millions. That scaling problem, more than any single materials challenge, is why micro-LED display commercialization has moved slower than the underlying LED physics alone would suggest, and why mass transfer rather than epitaxy is often the true gating step in a production ramp.

Blue and green micro-LEDs are grown as InGaN/GaN multiple-quantum-well stacks on sapphire or silicon substrates, while red emitters are more commonly grown as AlInGaP or InGaAs stacks on GaAs substrates because InGaN red emission at high indium content suffers from poor material quality. A typical active region uses quantum wells only a few nanometers thick, roughly 2 to 3 nm, stacked in multiple periods to balance radiative recombination against strain accumulation, and the resulting epitaxial wafer's wavelength uniformity across the growth run directly sets how much post-fabrication binning a display maker must do to match RGB sub-pixels. Lattice mismatch between the epitaxial layer and its growth substrate is the underlying constraint behind almost every material choice here, and it is exactly why red emitters have historically lagged blue and green in micro-LED maturity: InGaN growth on foreign substrates is comparatively forgiving of composition, while high-indium InGaN needed for red emission is not.

Mesa etching isolates each emitter electrically and optically, but shrinking the mesa toward a few-micrometer footprint expands the sidewall surface area relative to active-region volume, so surface recombination at the etched sidewall becomes the dominant non-radiative loss channel rather than a secondary one. Sidewall passivation, typically a thin dielectric deposited immediately after mesa etch and before air exposure lets surface states form, can recover a meaningful fraction of external quantum efficiency, and a mesa smaller than roughly 5 µm across is where this sidewall-dominated droop becomes the primary efficiency limiter rather than an academic concern. The etch chemistry itself matters as much as the passivation that follows it, since a rough or damaged sidewall creates more trap states for the passivation layer to compensate for, so mesa etch and passivation are increasingly co-developed as a single process module rather than two independent steps.

Contact metallization must spread current uniformly across a mesa that may be only a few micrometers wide while keeping specific contact resistance low enough that the contact itself does not dominate the diode's forward voltage. A transparent or semi-transparent p-contact combined with a reflective n-side mirror is common in top-emitting designs, and forward voltage in the 2.5 to 3.2 V range at typical display drive current density is a reasonable target once contact resistance and epitaxial quality are both under control. Because a display drives millions of these contacts in parallel, even a small contact-resistance variation across the wafer translates into visible brightness or color non-uniformity across the finished panel, so contact-metallization uniformity is tracked as closely as the epitaxial growth itself.

Mass transfer moves LED die from the growth wafer to the display backplane by one of several competing methods: elastomer-stamp pick-and-place, fluidic self-assembly into shaped wells, or laser lift-off that releases a whole array at once from a sapphire donor substrate. Each method trades throughput against placement accuracy, but every method is judged against the same yield bar, since a display with millions of sub-pixels needs a per-die transfer yield well above 99.9% before defect-repair strategies become economically practical rather than a last resort. Placement accuracy within roughly 1 µm is typically required so the transferred die lands within its intended backplane bond pad without shorting a neighboring sub-pixel.

Pixel pitch scaling is the single number that ties epitaxy, mesa size, and mass transfer together, because every step a display pitch shrinks demands a proportionally smaller mesa, tighter transfer placement accuracy, and less thermal or optical crosstalk budget between neighboring emitters. Large-format display pitch has moved from roughly 50 µm in early demonstration panels down toward 10 µm for near-term high-density panels, with sub-5 µm pitch discussed for augmented-reality microdisplays, and each step down in pitch pushes sidewall-dominated efficiency loss and transfer yield further to the front of the process-development list.

Achieving red, green, and blue emission on a single display can follow either a native-RGB path, transferring three separately grown epitaxial materials onto one backplane, or a color-conversion path, transferring only blue or ultraviolet emitters and converting a fraction of them to red and green with a quantum-dot or phosphor layer. Native RGB gives the highest theoretical efficiency per sub-pixel but triples the mass-transfer burden, while color conversion simplifies transfer to a single emitter type at the cost of conversion-layer efficiency loss and an added patterning step, and the two paths remain in active competition across the display industry rather than one having settled the question.

Process verification for micro-LED fabrication combines materials and electrical metrology at both the epitaxial-wafer stage and the transferred-array stage, since a defect invisible at wafer level can still show up as a dead or dim pixel after transfer. XPS confirms surface stoichiometry ahead of passivation deposition, AFM measures mesa sidewall roughness after etch, SIMS profiles dopant concentration through the epitaxial stack, Hall effect measurement confirms carrier concentration and mobility in the GaN or GaAs layers, four-point probe checks contact and current-spreading-layer sheet resistance, and each transferred die is finally screened on a Keithley source-measure unit against NIST-traceable current and voltage references before the panel is accepted.

Epitaxial growth (InGaN/GaN or AlInGaP on GaAs) → Mesa mask and etch → Sidewall passivation → Contact metallization (p/n) → Epitaxial-wafer test (XPS, AFM, SIMS, Hall effect) → Laser lift-off or stamp release from donor wafer → Mass transfer to backplane (pick-and-place / fluidic) → Bond and interconnect → Die-level electrical test (Keithley, NIST-traceable) → Defect repair and redundancy → Color conversion or RGB tiling → Panel qualification and release

Read micro-LED fabrication through an emissive-pixel engineering lens: a 2 to 3 nm quantum well, a mesa shrinking past the 5 µm sidewall-recombination threshold, a forward voltage near 2.5 to 3.2 V, mass-transfer yield above 99.9% per die with placement accuracy near 1 µm, and pixel pitch moving from 50 µm toward 10 µm and below are not independent numbers but one continuous chain from epitaxy to panel, verified end to end with XPS, AFM, SIMS, Hall effect, four-point probe, Keithley, and NIST-traceable references.