ML for Parasitic Extraction is the application of machine learning to predict resistance, capacitance, and inductance from layout 100-1000× faster than field solvers — where ML models trained on millions of extracted layouts predict wire resistance with <5% error, coupling capacitance with <10% error, and inductance with <15% error, enabling real-time parasitic estimation during routing that guides optimization decisions, achieving 10-20% better timing through parasitic-aware routing and reducing extraction time from hours to seconds for incremental changes through CNN-based 3D field approximation, GNN-based net-level prediction, and transfer learning across technology nodes, making ML-powered extraction essential for advanced nodes where parasitics dominate delay (60-80% of total) and traditional extraction becomes prohibitively expensive for billion-net designs requiring days of compute time.

Resistance Prediction:

• Wire Resistance: ML predicts sheet resistance and via resistance; <5% error vs field solver; considers width, thickness, temperature
• Contact Resistance: ML predicts contact resistance; <10% error; considers size, material, process variation
• Frequency Effects: ML models skin effect and proximity effect; >1GHz; <10% error; frequency-dependent resistance
• Temperature Effects: ML models resistance vs temperature; <5% error; critical for reliability

Capacitance Prediction:

• Self-Capacitance: ML predicts capacitance to ground; <5% error; considers geometry and dielectric
• Coupling Capacitance: ML predicts inter-wire coupling; <10% error; 3D field effects; critical for timing
• Fringe Capacitance: ML models fringe effects; <10% error; important for narrow wires
• Multi-Layer: ML handles 10-15 metal layers; complex 3D structures; <15% error

Inductance Prediction:

• Self-Inductance: ML predicts wire inductance; <15% error; important for power grid and high-speed signals
• Mutual Inductance: ML predicts coupling inductance; <20% error; affects crosstalk and signal integrity
• Frequency Range: ML models inductance from DC to 100GHz; multi-scale; challenging but feasible
• Return Path: ML considers return current path; affects inductance; 3D modeling required

CNN for 3D Field Approximation:

• Input: layout as 3D voxel grid; metal layers, vias, dielectrics; 64×64×16 to 256×256×32 resolution
• Architecture: 3D CNN or U-Net; predicts field distribution; 20-50 layers; 10-100M parameters
• Output: electric and magnetic fields; derive R, C, L; <10-15% error vs Maxwell solver
• Speed: millisecond inference; 1000-10000× faster than field solver; enables real-time extraction

GNN for Net-Level Prediction:

• Net Graph: nodes are wire segments and vias; edges represent connections; node features (width, length, layer)
• Parasitic Prediction: GNN predicts R, C, L for each segment; aggregates to net level; <10% error
• Scalability: handles millions of nets; linear scaling; efficient for large designs
• Hierarchical: block-level then net-level; enables billion-net designs

Incremental Extraction:

• Change Detection: ML identifies changed regions; focuses extraction on changes; 10-100× speedup for ECOs
• Impact Analysis: ML predicts which nets affected by changes; extracts only affected nets; 5-20× speedup
• Caching: ML caches extraction results; reuses for unchanged regions; 2-10× speedup
• Adaptive: ML adjusts extraction accuracy based on criticality; fast for non-critical, accurate for critical

Training Data:

• Field Solver Results: millions of 3D EM simulations; R, C, L values; diverse geometries and technologies
• Measurements: silicon measurements; validates models; real-world correlation
• Production Designs: billions of extracted nets; from past designs; diverse patterns
• Synthetic Data: generate synthetic layouts; controlled variations; augment training data

Model Architectures:

• 3D CNN: for field prediction; 64×64×16 input; 20-50 layers; 10-100M parameters
• GNN: for net-level prediction; 5-15 layers; 1-10M parameters
• Ensemble: combines multiple models; improves accuracy; reduces variance
• Physics-Informed: incorporates Maxwell equations; improves extrapolation

Integration with EDA Tools:

• Synopsys StarRC: ML-accelerated extraction; 10-100× speedup; <10% error; production-proven
• Cadence Quantus: ML for fast extraction; incremental and hierarchical; 5-20× speedup
• Siemens Calibre xACT: ML for parasitic extraction; 3D field approximation; growing adoption
• Ansys: ML surrogate models for EM extraction; 100-1000× speedup

Performance Metrics:

• Accuracy: <5% for resistance, <10% for capacitance, <15% for inductance; sufficient for timing analysis
• Speedup: 100-1000× faster than field solvers; enables real-time extraction during routing
• Scalability: handles billion-net designs; linear scaling; traditional extraction super-linear
• Memory: 1-10GB for million-net designs; efficient GPU implementation

Parasitic-Aware Routing:

• Real-Time Estimation: ML provides parasitic estimates during routing; guides decisions; 10-20% better timing
• What-If Analysis: quickly evaluate routing alternatives; 1000× faster than full extraction; enables exploration
• Optimization: ML guides routing to minimize parasitics; shorter wires, optimal spacing, layer assignment
• Trade-offs: ML balances parasitics, wirelength, congestion; Pareto-optimal solutions

Technology Scaling:

• Transfer Learning: models trained on one node transfer to similar nodes; 10-100× faster training
• Node-Specific: fine-tune for specific technology; 1000-10000 layouts; improves accuracy by 20-40%
• Multi-Node: single model handles multiple nodes; learns scaling trends; generalizes better
• Advanced Nodes: 3nm, 2nm, 1nm; parasitics dominate (60-80% of delay); ML critical

Advanced Packaging:

• 2.5D/3D: ML models parasitics in advanced packages; TSVs, interposers, RDL; <20% error
• Chiplet Interfaces: ML extracts parasitics for inter-chiplet connections; critical for performance
• Package-Level: ML handles chip-package co-extraction; holistic view; 30-50% accuracy improvement
• Heterogeneous: different materials and structures; challenging but feasible with ML

Challenges:

• 3D Complexity: full 3D extraction expensive; ML approximates; <10-15% error acceptable for optimization
• Frequency Dependence: R, C, L vary with frequency; requires multi-frequency models
• Process Variation: parasitics vary with process; ML models statistical behavior; ±10-20% variation
• Validation: must validate with measurements; silicon correlation; builds trust

Commercial Adoption:

• Leading-Edge: Intel, TSMC, Samsung using ML extraction; internal tools; significant speedup
• Fabless: Qualcomm, NVIDIA, AMD using ML for fast extraction; enables iteration
• EDA Vendors: Synopsys, Cadence, Siemens integrating ML; production-ready; growing adoption
• Startups: several startups developing ML extraction solutions; niche market

Best Practices:

• Hybrid Approach: ML for fast extraction; field solver for critical nets; best of both worlds
• Validate: always validate ML predictions with field solver; spot-check; ensures accuracy
• Incremental: use ML for incremental extraction; ECOs and design changes; 10-100× faster
• Continuous Learning: retrain on new designs; improves accuracy; adapts to new patterns

Cost and ROI:

• Tool Cost: ML extraction tools $50K-200K per year; justified by time savings
• Extraction Time: 100-1000× faster; reduces design cycle; $100K-1M value per project
• Timing Improvement: 10-20% through parasitic-aware routing; higher frequency; $10M-100M value
• Iteration: enables more iterations; better optimization; 20-40% QoR improvement

ML for Parasitic Extraction represents the acceleration of RC extraction — by predicting resistance with <5% error and capacitance with <10% error 100-1000× faster than field solvers, ML enables real-time parasitic estimation during routing that guides optimization decisions and achieves 10-20% better timing, reducing extraction time from hours to seconds for incremental changes and making ML-powered extraction essential for advanced nodes where parasitics dominate delay and traditional extraction becomes prohibitively expensive for billion-net designs.');