<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Strained silicon: stretch the lattice and carriers move faster</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Deforming the channel raises mobility &#8212; more drive current without shrinking the transistor</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Strain vs mobility</text><text x="32" y="106" fill="#8b949e" font-size="10.5">spacing between atoms sets carrier speed</text><!-- relaxed lattice --><text x="34" y="128" fill="#8b949e" font-size="9.5">relaxed Si</text><g fill="#6f8fb0"><circle cx="44" cy="146" r="3.2"/><circle cx="64" cy="146" r="3.2"/><circle cx="84" cy="146" r="3.2"/><circle cx="104" cy="146" r="3.2"/><circle cx="44" cy="166" r="3.2"/><circle cx="64" cy="166" r="3.2"/><circle cx="84" cy="166" r="3.2"/><circle cx="104" cy="166" r="3.2"/></g><circle cx="120" cy="156" r="2.6" fill="#e0b13a"/><line x1="120" y1="156" x2="134" y2="156" stroke="#e0b13a" stroke-width="1.3" marker-end="url(#s1)"/><text x="140" y="159" fill="#e0913a" font-size="8">slower</text><!-- strained lattice (stretched) --><text x="34" y="196" fill="#7ee6c0" font-size="9.5">strained (stretched)</text><g fill="#7ee6c0"><circle cx="44" cy="214" r="3.2"/><circle cx="70" cy="214" r="3.2"/><circle cx="96" cy="214" r="3.2"/><circle cx="122" cy="214" r="3.2"/><circle cx="44" cy="238" r="3.2"/><circle cx="70" cy="238" r="3.2"/><circle cx="96" cy="238" r="3.2"/><circle cx="122" cy="238" r="3.2"/></g><circle cx="138" cy="226" r="2.6" fill="#34d399"/><line x1="138" y1="226" x2="164" y2="226" stroke="#34d399" stroke-width="1.6" marker-end="url(#s2)"/><text x="170" y="229" fill="#34d399" font-size="8">faster</text><text x="32" y="272" fill="#adb5bd" font-size="9.5">Wider atomic spacing reshapes the</text><text x="32" y="287" fill="#adb5bd" font-size="9.5">energy bands so electrons scatter</text><text x="32" y="302" fill="#adb5bd" font-size="9.5">less and drift faster for the same</text><text x="32" y="317" fill="#adb5bd" font-size="9.5">field. Higher &#181; &#8594; higher drive current.</text><text x="32" y="340" fill="#8b949e" font-size="9.5">&#181; = mobility &#183; sets I<tspan font-size="6.5" dy="2">on</tspan><tspan dy="-2"> at fixed voltage</tspan></text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; Opposite strain per type</text><text x="279" y="106" fill="#8b949e" font-size="10.5">electrons and holes want different lattices</text><!-- nMOS tensile --><text x="279" y="128" fill="#34d399" font-size="9.5" font-weight="700">nMOS &#8212; tensile (pull apart)</text><rect x="300" y="150" width="160" height="34" rx="2" fill="#1c2733" stroke="#233041"/><rect x="336" y="150" width="88" height="10" fill="#34d399" opacity="0.85"/><rect x="352" y="138" width="56" height="10" rx="2" fill="#d08a4a"/><text x="380" y="146" fill="#f0d9b5" font-size="7" text-anchor="middle">gate</text><line x1="336" y1="167" x2="316" y2="167" stroke="#34d399" stroke-width="1.4" marker-end="url(#s2)"/><line x1="424" y1="167" x2="444" y2="167" stroke="#34d399" stroke-width="1.4" marker-end="url(#s2)"/><text x="380" y="179" fill="#8b949e" font-size="7.5" text-anchor="middle">channel stretched &#8594; fast electrons</text><!-- pMOS compressive --><text x="279" y="210" fill="#e0913a" font-size="9.5" font-weight="700">pMOS &#8212; compressive (SiGe pushes in)</text><rect x="300" y="232" width="160" height="34" rx="2" fill="#1c2733" stroke="#233041"/><rect x="300" y="232" width="34" height="34" fill="#b8732e"/><rect x="426" y="232" width="34" height="34" fill="#b8732e"/><text x="317" y="252" fill="#f0d9b5" font-size="7" text-anchor="middle">SiGe</text><text x="443" y="252" fill="#f0d9b5" font-size="7" text-anchor="middle">SiGe</text><rect x="336" y="232" width="88" height="10" fill="#e0913a" opacity="0.85"/><rect x="352" y="220" width="56" height="10" rx="2" fill="#d08a4a"/><text x="380" y="228" fill="#f0d9b5" font-size="7" text-anchor="middle">gate</text><line x1="342" y1="249" x2="360" y2="249" stroke="#e0913a" stroke-width="1.4" marker-end="url(#s3)"/><line x1="418" y1="249" x2="400" y2="249" stroke="#e0913a" stroke-width="1.4" marker-end="url(#s3)"/><text x="380" y="279" fill="#8b949e" font-size="7.5" text-anchor="middle">channel squeezed &#8594; fast holes</text><text x="279" y="300" fill="#adb5bd" font-size="9.5">Bigger Ge atoms in the source/drain</text><text x="279" y="315" fill="#adb5bd" font-size="9.5">compress the pMOS channel; a tensile</text><text x="279" y="330" fill="#adb5bd" font-size="9.5">cap film stretches the nMOS one.</text><text x="279" y="345" fill="#8b949e" font-size="9.5">Same die, opposite strain, both faster.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; How strain is built in</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the process levers &#8212; since ~90nm</text><circle cx="532" cy="126" r="2.4" fill="#b8732e"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Embedded SiGe S/D (pMOS)</text><text x="542" y="143" fill="#8b949e" font-size="9">recessed source/drain refilled with</text><text x="542" y="156" fill="#8b949e" font-size="9">SiGe to compress the channel.</text><circle cx="532" cy="176" r="2.4" fill="#34d399"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Tensile CESL nitride (nMOS)</text><text x="542" y="193" fill="#8b949e" font-size="9">a stressed contact-etch-stop liner</text><text x="542" y="206" fill="#8b949e" font-size="9">pulls the channel into tension.</text><circle cx="532" cy="226" r="2.4" fill="#9fd8ef"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Stress-memorization anneal</text><text x="542" y="243" fill="#8b949e" font-size="9">strain locked in during recrystallization</text><text x="542" y="256" fill="#8b949e" font-size="9">of the source/drain.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#e0b13a" font-size="10" font-weight="700">Why it stuck around</text><text x="536" y="306" fill="#adb5bd" font-size="9">A "free" performance boost: more speed</text><text x="536" y="320" fill="#adb5bd" font-size="9">at the same gate length. Still used inside</text><text x="536" y="334" fill="#adb5bd" font-size="9">FinFET and nanosheet channels today, now</text><text x="536" y="348" fill="#adb5bd" font-size="9">via 3D-aware stressor engineering.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Tensile &#8594; nMOS</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Stretching the lattice speeds up</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">electrons &#8212; the majority carrier.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#e0913a" font-size="11" font-weight="700">Compressive &#8594; pMOS</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">Squeezing the lattice speeds up</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">holes &#8212; via embedded SiGe.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Mobility = speed</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Higher &#181; lifts drive current without</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">a smaller, leakier transistor.</text><defs><marker id="s1" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#e0b13a"/></marker><marker id="s2" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#34d399"/></marker><marker id="s3" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#e0913a"/></marker></defs></svg>

Mobility Modeling is the TCAD simulation of charge carrier drift mobility (μ) as a function of doping concentration, electric field, temperature, interface quality, and crystal strain — predicting the carrier transport speed that determines transistor drive current (I_on), switching speed (f_T), and energy efficiency, using Matthiessen's Rule to combine the independent contributions of phonon scattering, ionized impurity scattering, surface roughness scattering, and other mechanisms into a total effective mobility.

What Is Carrier Mobility?

Mobility quantifies how fast a carrier drifts in response to an electric field:

μ = v_drift / E (units: cm²/V·s)

Higher mobility → faster carrier response → faster transistor switching at lower supply voltage.

Matthiessen's Rule — Combining Scattering Mechanisms

Each scattering mechanism independently limits mobility. The total mobility is their harmonic sum:

1/μ_total = 1/μ_phonon + 1/μ_impurity + 1/μ_surface + 1/μ_other

The mechanism with the lowest individual mobility dominates the total (bottleneck principle).

Low-Field Mobility Models

Phonon Scattering Component (μ_phonon): Acoustic and optical phonon scattering dominate in lightly doped silicon at room temperature. Temperature dependence follows μ_phonon ∝ T^(-3/2) for acoustic phonons — mobility degrades with increasing temperature, the fundamental reason processor performance drops under thermal throttling.

Ionized Impurity Scattering Component (μ_imp): Coulomb interaction with ionized donor and acceptor atoms. Concentration dependence modeled by Masetti et al.: μ = μ_min + (μ_max - μ_min) / (1 + (N/N_ref)^α) Where N = total ionized impurity concentration. Mobility drops sharply above ~10¹⁷ cm⁻³ doping — the key trade-off between conductivity (needs high doping) and mobility (degraded by high doping).

Surface Roughness Scattering Component (μ_sr): Dominates in the MOSFET inversion layer under high vertical fields. The Lombardi model adds a field-dependent surface mobility component: μ_sr ∝ 1/(E_perp)² × 1/δ_rms² Where E_perp = perpendicular field and δ_rms = oxide interface roughness amplitude. As gate overdrive increases, E_perp increases, confining carriers tighter against the rough interface → mobility decreases. This "mobility degradation" is why measured MOSFET mobility peaks at low gate voltage and falls at high VGS.

High-Field Velocity Saturation

At high lateral electric fields, carriers emit optical phonons faster than they gain energy from the field — reaching a saturation velocity:

v_sat(Si electrons) ≈ 10⁷ cm/s

The Caughey-Thomas model transitions smoothly from ohmic to saturated velocity:

v(E) = μ_low × E / [1 + (μ_low × E / v_sat)^β]^(1/β)

Velocity saturation is the fundamental limit of drive current in nanometer-scale transistors where the entire channel is near saturation.

Quantum Confinement Corrections

In FinFETs and nanosheet FETs with body thickness < 10 nm, quantum confinement shifts the energy subbands and modifies carrier occupancy relative to bulk. Effective mass and density of states corrections to the mobility model are required to avoid overestimating drive current.

Why Mobility Modeling Matters

• Drive Current Prediction: I_on ∝ μ × Cox × (VGS - Vth) × V_drain for long channel. Mobility accuracy directly determines drive current prediction accuracy — 10% mobility error → 10% drive current error → incorrect power/performance model.
• Process Optimization: Simulation-guided mobility optimization identifies the trade-off between higher channel doping (needed to suppress short-channel effects) and lower channel mobility (consequence of higher impurity scattering). Finding the optimal pocket implant dose requires accurate mobility modeling.
• Strain Engineering Validation: The mobility enhancement from strained silicon channels must be accurately predicted to justify the process integration cost. Piezoresistance models and band structure-derived mobility enhancements are validated against measurement in simulation.
• Self-Heating Coupling: In FinFETs at high power density, junction temperature rises substantially. Since μ_phonon ∝ T^(-3/2), self-heating reduces carrier mobility, further reducing drive current — a negative feedback that simulation must capture for accurate I_on–I_off modeling under realistic operating conditions.

Tools

• Synopsys Sentaurus Device: Full mobility model library including Masetti, Lombardi surface model, high-field saturation, quantum correction, and strain-dependent piezoresistance.
• Silvaco Atlas: Device simulator with comprehensive mobility models for Si, SiGe, Ge, III-V materials.
• nextnano: k·p-based quantum transport simulation including mobility in nanostructures.

Mobility Modeling is calculating the speed limit for charge carriers — summing all the scattering forces that impede carrier drift through the transistor channel to predict the drive current and switching speed that determine whether a chip delivers its target performance, guiding process engineers to the optimal combination of doping, strain, interface quality, and geometry that maximizes carrier speed at minimum power consumption.