<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Strained silicon: stretch the lattice and carriers move faster</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Deforming the channel raises mobility &#8212; more drive current without shrinking the transistor</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Strain vs mobility</text><text x="32" y="106" fill="#8b949e" font-size="10.5">spacing between atoms sets carrier speed</text><!-- relaxed lattice --><text x="34" y="128" fill="#8b949e" font-size="9.5">relaxed Si</text><g fill="#6f8fb0"><circle cx="44" cy="146" r="3.2"/><circle cx="64" cy="146" r="3.2"/><circle cx="84" cy="146" r="3.2"/><circle cx="104" cy="146" r="3.2"/><circle cx="44" cy="166" r="3.2"/><circle cx="64" cy="166" r="3.2"/><circle cx="84" cy="166" r="3.2"/><circle cx="104" cy="166" r="3.2"/></g><circle cx="120" cy="156" r="2.6" fill="#e0b13a"/><line x1="120" y1="156" x2="134" y2="156" stroke="#e0b13a" stroke-width="1.3" marker-end="url(#s1)"/><text x="140" y="159" fill="#e0913a" font-size="8">slower</text><!-- strained lattice (stretched) --><text x="34" y="196" fill="#7ee6c0" font-size="9.5">strained (stretched)</text><g fill="#7ee6c0"><circle cx="44" cy="214" r="3.2"/><circle cx="70" cy="214" r="3.2"/><circle cx="96" cy="214" r="3.2"/><circle cx="122" cy="214" r="3.2"/><circle cx="44" cy="238" r="3.2"/><circle cx="70" cy="238" r="3.2"/><circle cx="96" cy="238" r="3.2"/><circle cx="122" cy="238" r="3.2"/></g><circle cx="138" cy="226" r="2.6" fill="#34d399"/><line x1="138" y1="226" x2="164" y2="226" stroke="#34d399" stroke-width="1.6" marker-end="url(#s2)"/><text x="170" y="229" fill="#34d399" font-size="8">faster</text><text x="32" y="272" fill="#adb5bd" font-size="9.5">Wider atomic spacing reshapes the</text><text x="32" y="287" fill="#adb5bd" font-size="9.5">energy bands so electrons scatter</text><text x="32" y="302" fill="#adb5bd" font-size="9.5">less and drift faster for the same</text><text x="32" y="317" fill="#adb5bd" font-size="9.5">field. Higher &#181; &#8594; higher drive current.</text><text x="32" y="340" fill="#8b949e" font-size="9.5">&#181; = mobility &#183; sets I<tspan font-size="6.5" dy="2">on</tspan><tspan dy="-2"> at fixed voltage</tspan></text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; Opposite strain per type</text><text x="279" y="106" fill="#8b949e" font-size="10.5">electrons and holes want different lattices</text><!-- nMOS tensile --><text x="279" y="128" fill="#34d399" font-size="9.5" font-weight="700">nMOS &#8212; tensile (pull apart)</text><rect x="300" y="150" width="160" height="34" rx="2" fill="#1c2733" stroke="#233041"/><rect x="336" y="150" width="88" height="10" fill="#34d399" opacity="0.85"/><rect x="352" y="138" width="56" height="10" rx="2" fill="#d08a4a"/><text x="380" y="146" fill="#f0d9b5" font-size="7" text-anchor="middle">gate</text><line x1="336" y1="167" x2="316" y2="167" stroke="#34d399" stroke-width="1.4" marker-end="url(#s2)"/><line x1="424" y1="167" x2="444" y2="167" stroke="#34d399" stroke-width="1.4" marker-end="url(#s2)"/><text x="380" y="179" fill="#8b949e" font-size="7.5" text-anchor="middle">channel stretched &#8594; fast electrons</text><!-- pMOS compressive --><text x="279" y="210" fill="#e0913a" font-size="9.5" font-weight="700">pMOS &#8212; compressive (SiGe pushes in)</text><rect x="300" y="232" width="160" height="34" rx="2" fill="#1c2733" stroke="#233041"/><rect x="300" y="232" width="34" height="34" fill="#b8732e"/><rect x="426" y="232" width="34" height="34" fill="#b8732e"/><text x="317" y="252" fill="#f0d9b5" font-size="7" text-anchor="middle">SiGe</text><text x="443" y="252" fill="#f0d9b5" font-size="7" text-anchor="middle">SiGe</text><rect x="336" y="232" width="88" height="10" fill="#e0913a" opacity="0.85"/><rect x="352" y="220" width="56" height="10" rx="2" fill="#d08a4a"/><text x="380" y="228" fill="#f0d9b5" font-size="7" text-anchor="middle">gate</text><line x1="342" y1="249" x2="360" y2="249" stroke="#e0913a" stroke-width="1.4" marker-end="url(#s3)"/><line x1="418" y1="249" x2="400" y2="249" stroke="#e0913a" stroke-width="1.4" marker-end="url(#s3)"/><text x="380" y="279" fill="#8b949e" font-size="7.5" text-anchor="middle">channel squeezed &#8594; fast holes</text><text x="279" y="300" fill="#adb5bd" font-size="9.5">Bigger Ge atoms in the source/drain</text><text x="279" y="315" fill="#adb5bd" font-size="9.5">compress the pMOS channel; a tensile</text><text x="279" y="330" fill="#adb5bd" font-size="9.5">cap film stretches the nMOS one.</text><text x="279" y="345" fill="#8b949e" font-size="9.5">Same die, opposite strain, both faster.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; How strain is built in</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the process levers &#8212; since ~90nm</text><circle cx="532" cy="126" r="2.4" fill="#b8732e"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Embedded SiGe S/D (pMOS)</text><text x="542" y="143" fill="#8b949e" font-size="9">recessed source/drain refilled with</text><text x="542" y="156" fill="#8b949e" font-size="9">SiGe to compress the channel.</text><circle cx="532" cy="176" r="2.4" fill="#34d399"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Tensile CESL nitride (nMOS)</text><text x="542" y="193" fill="#8b949e" font-size="9">a stressed contact-etch-stop liner</text><text x="542" y="206" fill="#8b949e" font-size="9">pulls the channel into tension.</text><circle cx="532" cy="226" r="2.4" fill="#9fd8ef"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Stress-memorization anneal</text><text x="542" y="243" fill="#8b949e" font-size="9">strain locked in during recrystallization</text><text x="542" y="256" fill="#8b949e" font-size="9">of the source/drain.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#e0b13a" font-size="10" font-weight="700">Why it stuck around</text><text x="536" y="306" fill="#adb5bd" font-size="9">A "free" performance boost: more speed</text><text x="536" y="320" fill="#adb5bd" font-size="9">at the same gate length. Still used inside</text><text x="536" y="334" fill="#adb5bd" font-size="9">FinFET and nanosheet channels today, now</text><text x="536" y="348" fill="#adb5bd" font-size="9">via 3D-aware stressor engineering.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Tensile &#8594; nMOS</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Stretching the lattice speeds up</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">electrons &#8212; the majority carrier.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#e0913a" font-size="11" font-weight="700">Compressive &#8594; pMOS</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">Squeezing the lattice speeds up</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">holes &#8212; via embedded SiGe.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Mobility = speed</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Higher &#181; lifts drive current without</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">a smaller, leakier transistor.</text><defs><marker id="s1" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#e0b13a"/></marker><marker id="s2" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#34d399"/></marker><marker id="s3" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#e0913a"/></marker></defs></svg>

Mobility variation is the spread in carrier transport efficiency across devices caused by local differences in scattering, strain, and interface quality - it directly modulates drive current and timing at fixed geometry and bias.

What Is Mobility Variation?

• Definition: Device-to-device and location-dependent fluctuation in effective electron or hole mobility.
• Physical Contributors: Surface roughness scattering, phonon interactions, Coulomb scattering, and stress variation.
• Electrical Impact: Idsat spread, gm variation, and delay distribution broadening.
• Correlation: Often coupled with strain and process-induced local geometry effects.

Why Mobility Variation Matters

• Timing Spread: Logic path delays shift even when Vth targets are met.
• Analog Gain Variance: Transconductance uncertainty degrades precision circuits.
• Power-Performance Tradeoff: Mobility tails influence both speed bins and energy targets.
• Model Accuracy: Needs explicit treatment in compact models for robust signoff.
• Yield Sensitivity: Combined with Vth variation, mobility spread expands failure tails.

How It Is Used in Practice

• Extraction: Use dedicated test structures to separate mobility from threshold effects.
• Statistical Modeling: Include mobility sigma and correlation with other parameters.
• Mitigation: Optimize strain engineering, interface quality, and layout context uniformity.

Mobility variation is a fundamental transport-level variability source that shapes real silicon speed beyond nominal design assumptions - robust performance prediction requires mobility-aware statistical modeling.