Molybdenum Gate Electrodes are the alternative gate metal material being developed to replace the complex multi-layer TiN/TiAl/TiN gate stacks used in current high-k/metal-gate CMOS — offering a single metal solution with tunable work function through nitrogen or silicon incorporation, lower gate resistance due to simpler fill in narrow gate trenches, and a cleaner interface with high-k dielectrics, potentially simplifying the replacement metal gate (RMG) process while improving both NMOS and PMOS transistor performance.
Why Replace Current Gate Metals
- Current HKMG: Multiple thin metal layers (TiN, TiAl, TiAlC, TaN) → many deposition steps.
- GAA nanosheet: Gate wraps around channels → must fill extremely narrow gaps between sheets.
- Multi-layer stack: TiN(2nm) + TiAl(1nm) + TiN(2nm) + W-fill = 5nm+ consumed → insufficient room in 5nm gap.
- Molybdenum: Single metal → ALD → fills narrow gaps conformally → simpler process.
Work Function Engineering
| Material | Work Function (eV) | Band Edge | Application |
|---|---|---|---|
| TiN | 4.5-4.7 | Mid-gap | Baseline (neither N nor P optimized) |
| TiAl/TiAlC | 4.0-4.3 | NMOS (conduction band) | NMOS WF metal |
| Mo | 4.5-4.7 | Mid-gap (tunable) | Starting point |
| Mo₂N | 4.2-4.4 | Near NMOS target | N-type tuning |
| MoSi₂ | 4.7-4.9 | Near PMOS target | P-type tuning |
Work Function Tuning Strategy
- Pure Mo: ~4.6 eV → mid-gap → need shift for both NMOS and PMOS.
- NMOS: Incorporate nitrogen → Mo₂N → shifts toward 4.2 eV → closer to Si conduction band.
- PMOS: Incorporate silicon or use Mo/oxide interface dipole → shifts toward 4.9 eV.
- Alternative: Dipole engineering at Mo/HfO₂ interface with thin La₂O₃ (NMOS) or Al₂O₃ (PMOS) interlayers.
ALD Molybdenum
- Precursor: MoF₆, MoCl₅, or Mo(CO)₆.
- Co-reactant: H₂ plasma or Si₂H₆.
- Growth rate: 0.03-0.06 nm/cycle → precise thickness control.
- Conformality: >95% in high-AR structures → fills between nanosheets.
- Resistivity: 12-20 µΩ·cm (ALD) vs. 8-10 µΩ·cm (PVD) → acceptable.
Advantages Over TiN/TiAl Stack
| Property | Multi-layer TiN/TiAl | Single Mo-based |
|---|---|---|
| Number of deposition steps | 4-6 layers | 1-2 layers |
| Minimum gate fill thickness | 5-8nm | 2-3nm |
| Gate resistance | Higher (many thin interfaces) | Lower (single metal) |
| GAA compatibility | Challenging (narrow gaps) | Better (simpler fill) |
| Process complexity | Very high | Moderate |
| Fluorine residue risk | Low (Cl-based precursors) | Higher (if MoF₆ used) |
Challenges
| Challenge | Issue | Status |
|---|---|---|
| Fluorine contamination | MoF₆ precursor → F attacks high-k | Alternative precursors (Cl-based) |
| Work function range | Pure Mo mid-gap → need WF modifiers | Nitrogen/Si doping, dipole layers |
| Reliability (PBTI/NBTI) | Mo/HfO₂ interface not as mature as TiN/HfO₂ | Active research |
| Industry inertia | TiN/TiAl well-established, extensive knowledge base | Gradual transition |
Roadmap
- N3/N2 (2024-2025): TiN/TiAl stack still baseline, but Mo under development.
- A14/A10 (2026-2028): Mo expected for at least one electrode (likely NMOS first).
- Beyond A10: Full Mo gate integration for both NMOS/PMOS likely.
Molybdenum gate electrodes represent the next major material transition in CMOS front-end processing — by replacing the increasingly unwieldy multi-layer TiN/TiAl gate stacks with a simpler single-metal solution that offers tunable work function and superior gap-fill in the extremely tight spaces of GAA nanosheet transistors, Mo gates address both the process complexity and the physical scaling limitations that are pushing current gate metal technology to its breaking point.
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.