The metal-oxide-semiconductor field-effect transistor is the foundational active device in modern integrated circuits, and every aspect of its behavior can be captured by equations that evolved over six decades, from Shockley's gradual-channel approximation through the Pao-Sah double-integral model and Brews's charge-sheet approximation to the Berkeley BSIM family, the NXP/TU Delft PSP surface-potential model, and the Enz-Krummenacher-Vittoz EKV charge-based framework that serve as industry-standard compact models today. Every transistor in a billion-device chip is instantiated through one of these models, and the fidelity of its equations determines whether simulation predicts silicon behavior within the margins that separate first-pass success from costly re-spin.

The threshold voltage equation encodes the gate voltage required to invert the semiconductor surface and initiate strong inversion. For an NMOS on p-type substrate, $V_{th} = V_{FB} + 2\phi_F + \gamma\sqrt{2\phi_F + V_{SB}}$, where $V_{FB} = \phi_{ms} - Q_{ox}/C_{ox}$ is the flat-band voltage set by the metal-semiconductor work-function difference and oxide charge, $\phi_F = (kT/q)\ln(N_A/n_i)$ is the Fermi potential, $\gamma = \sqrt{2q\epsilon_{si}N_A}/C_{ox}$ is the body-effect coefficient, and $V_{SB}$ is source-to-body voltage. Shockley and Sah established that inversion occurs when $\psi_s = 2\phi_F$. In advanced nodes, $V_{FB}$ is engineered through work-function metal selection (TiN, TiAl, TaN), and the interface dipole at the high-k boundary adds a component that Hobbs quantified as dependent on areal oxygen density difference.

The long-channel drain current follows Shockley's gradual-channel approximation in two operating regions. In the linear region, $I_D = \mu_n C_{ox} (W/L) [(V_{GS}-V_{th})V_{DS} - V_{DS}^2/2]$, where the quadratic term captures the non-uniform inversion charge thinning toward the drain. Setting $\partial I_D/\partial V_{DS} = 0$ yields the saturation voltage $V_{DS,sat} = V_{GS} - V_{th}$, and the saturation current becomes $I_D = (\mu_n C_{ox}/2)(W/L)(V_{GS}-V_{th})^2(1+\lambda V_{DS})$, where $\lambda$ is the channel-length modulation parameter giving output resistance $r_o = 1/(\lambda I_D)$. Tsividis's textbook shows $\lambda$ depends on bias and process parameters; modern compact models replace it with physics-based formulations.

The body effect modulates threshold voltage through source-body bias, affecting stacked transistors and source followers. When $V_{SB} > 0$, the depletion region widens, adding charge $\Delta Q_{dep} = -\gamma C_{ox}(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F})$ that raises $V_{th}$. The coefficient $\gamma$ ranges from 0.3 to 0.8 V$^{1/2}$ in bulk CMOS, producing 200 to 400 mV threshold shift for $V_{SB} = 1$ V. In SOI and FinFET technologies, the fully depleted thin body greatly reduces this effect.

Subthreshold conduction governs leakage power through diffusion of minority carriers below threshold. The current is $I_D = I_0 \exp(V_{GS}/(nV_T))(1 - \exp(-V_{DS}/V_T))$, where $V_T = kT/q \approx 26$ mV, $n = 1 + C_{dep}/C_{ox}$ is the ideality factor, and $I_0 \propto (W/L)\mu_n C_{ox} n V_T^2$. The subthreshold swing $SS = n V_T \ln(10) \approx 60$ mV/dec at room temperature for $n = 1$, reaching 70 to 90 mV/dec in practice. This 60 mV/dec limit is thermodynamic, arising from the Boltzmann distribution; overcoming it requires tunnel FETs or ferroelectric negative capacitance.

Velocity saturation fundamentally changes the current-voltage relationship in short-channel devices. Drift velocity saturates at $v_{sat} \approx 10^7$ cm/s for electrons, modeled as $v = \mu E / (1 + E/E_{crit})$ with $E_{crit} = v_{sat}/\mu \approx 5 \times 10^4$ V/cm. The velocity-saturated current becomes linear in overdrive: $I_D = W C_{ox} v_{sat} (V_{GS} - V_{th} - V_{DS,sat})$. BSIM4 uses a unified $V_{DS,sat} = (V_{GS}-V_{th}) \cdot v_{sat}L / ((V_{GS}-V_{th}) + v_{sat}L/\mu)$ that interpolates between long-channel quadratic and short-channel linear regimes.

Drain-induced barrier lowering reduces threshold voltage as drain bias increases in short-channel devices. DIBL occurs because the drain depletion region extends toward the source, lowering the potential barrier. The threshold shift is $\Delta V_{th} = -\eta V_{DS}$, where $\eta$ is typically 20 to 150 mV/V. Taur and Ning showed DIBL depends exponentially on $L/l$ where $l = \sqrt{\epsilon_{si} t_{ox} x_j / \epsilon_{ox}}$ is the natural length; when $L < 5l$ to $7l$, DIBL becomes unacceptable. FinFET and GAA architectures suppress DIBL to below 30 mV/V at 12 to 15 nm gate lengths by wrapping the gate around thin fins or nanosheets.

Channel-length modulation gives finite output resistance that limits voltage gain in analog circuits. The pinch-off point moves toward the source as $V_{DS}$ increases, with $\lambda \propto 1/L$. For 1 $\mu$m NMOS, $\lambda \approx 0.05$ V$^{-1}$; at 100 nm, $\lambda \approx 0.3$ V$^{-1}$. Cascoding achieves $r_{out} \approx g_m r_o^2$, recovering gain at the cost of headroom. BSIM4 models CLM through parameters PCLM, PDIBLC1, PDIBLC2, and DROUT.

Hot carrier effects arise when electrons near the drain gain energy exceeding the Si-SiO2 barrier height. Impact ionization generates substrate current $I_{sub} = (I_D / l_i) \alpha_i \exp(-\phi_i/(qE_{max}l_i))$, while gate injection creates interface traps that shift $V_{th}$ over time. The Hu group at Berkeley developed the lucky-electron model, with reliability lifetime $\tau \propto (I_{sub}/I_D)^{-n}$. Dennard scaling rules originally maintained constant fields, but their breakdown left aggressive fields that make hot-carrier reliability a timing guard-band constraint.

Gate oxide tunneling increases exponentially below 2 nm thickness, driving the transition to high-k dielectrics. Direct tunneling follows $J_{DT} \propto E_{ox}^2 \exp(-B/E_{ox})$, reaching 100 A/cm$^2$ at $t_{ox} = 1.2$ nm. HfO2 ($\kappa \approx 22$) provides $EOT = t_{high-k} \cdot (\epsilon_{SiO2}/\epsilon_{high-k})$, dramatically reducing leakage with a physically thicker film. A thin SiO2 interfacial layer (0.5 to 0.8 nm) sets a practical $EOT$ floor around 0.7 to 0.9 nm.

Narrow-width effects modify threshold voltage through fringing fields near shallow-trench isolation edges. In STI processes, the gate wraps around active-region corners, lowering $V_{th}$ for narrow devices (inverse narrow-width effect), opposing the classical effect seen in LOCOS. The shift can reach 50 to 100 mV, requiring STI-edge doping implants and BSIM4 width-dependent corrections.

Mobility degradation from vertical and lateral fields reduces current below the ideal prediction. The effective mobility follows the universal mobility curve established by Takagi: Coulomb scattering dominates at low fields, phonon scattering ($\mu \propto E_{eff}^{-1/3}$) at moderate fields, and surface roughness scattering ($\mu \propto E_{eff}^{-2}$) at high fields. Compact models use $\mu_{eff} = \mu_0 / (1 + \theta_1(V_{GS}-V_{th}) + \theta_2(V_{GS}-V_{th})^2)$.

The gate capacitance varies dramatically with bias, not behaving as a simple parallel-plate capacitor. In accumulation, $C_{gg} \approx C_{ox}$; in depletion, $C_{dep} = \epsilon_{si}/x_d$ appears in series, reducing total capacitance; in strong inversion, the inversion charge screens the substrate, recovering nearly $C_{ox}$, but quantum-mechanical confinement pushes the charge centroid 0.5 to 1.0 nm below the interface, adding an effective series capacitance. Overlap capacitances $C_{ov} = C_{ox} \times L_{ov}$ add bias-independent parasitics.

Junction capacitances between source/drain and body contribute voltage-dependent node loading. The source-body capacitance $C_{SB} = C_{j0,SB}/(1 + V_{SB}/\phi_{bi})^{m_j}$ has $\phi_{bi} \approx 0.7$ to $0.9$ V and $m_j = 0.5$ for abrupt junctions. BSIM4 separates bottom-plate and sidewall components with distinct $C_{j0}$ and $m_j$ for source-side, drain-side, gate-edge, and STI-edge contributions.

The Miller effect multiplies gate-drain capacitance by voltage gain, dominating high-frequency amplifier performance. During switching, $C_{gd}$ must charge through $(1 + A_v)$ times the input swing, creating a dominant pole. In CMOS inverters, this produces the Miller plateau in gate-voltage waveforms, slowing transitions through the high-gain region.

Charge-based models partition inversion charge between source and drain using physical conservation laws. The Ward-Dutton scheme assigns channel charge fractions based on the potential profile: approximately 50/50 in linear, shifting to 60/40 or 67/33 source/drain in saturation. The older Meyer model defines non-reciprocal capacitances that violate charge conservation, causing non-physical charge pumping in SPICE. Modern models (BSIM4, PSP, EKV) compute terminal charges as continuous functions, then derive capacitances as partial derivatives, ensuring conservation by construction.

Transconductance $g_m$ is the central figure of merit for amplifier design. In saturation, $g_m = \partial I_D / \partial V_{GS} = \mu_n C_{ox} (W/L)(V_{GS}-V_{th})$, or equivalently $g_m = \sqrt{2\mu_n C_{ox}(W/L)I_D}$. In velocity-saturated devices, $g_m \approx W C_{ox} v_{sat}$, becoming independent of overdrive. The transconductance efficiency $g_m/I_D$ peaks at $1/(nV_T) \approx 25$ to $30$ V$^{-1}$ in weak inversion and decreases as $2/(V_{GS}-V_{th})$ in strong inversion. The EKV model by Enz, Krummenacher, and Vittoz is built around continuous $g_m/I_D$ methodology spanning all inversion regimes.

Output conductance $g_{ds}$ limits the intrinsic voltage gain a single transistor delivers. Defined as $g_{ds} = \partial I_D / \partial V_{DS}$, it gives intrinsic gain $A_v = g_m/g_{ds} = g_m r_o$. For 180 nm, $A_v \approx 100$ (40 dB); at 28 nm, roughly 13 (22 dB). This gain erosion motivates cascoding, gain-boosting, and feedback architectures in analog design at advanced nodes.

The unity-gain frequency determines the maximum frequency at which a MOSFET provides current gain. Defined as $f_T = g_m / (2\pi C_{gg})$ where $C_{gg} = C_{gs} + C_{gd}$, for long channels $f_T = \mu(V_{GS}-V_{th})/(2\pi L^2)$, and for velocity-saturated devices $f_T \approx v_{sat}/(2\pi L)$, giving 100 to 300 GHz for $L$ = 20 to 60 nm. The maximum oscillation frequency $f_{max} = f_T / (2\sqrt{R_g(g_{ds}/g_m + 2\pi f_T C_{gd} R_g)})$ includes gate resistance and typically reaches 1.5 to 2 times $f_T$.

NMOS and PMOS transistors differ primarily in carrier mobility, making complementary design both necessary and nuanced. Electron mobility $\mu_n \approx 400$ to $500$ cm$^2$/(V$\cdot$s) is roughly 2 to 3 times hole mobility $\mu_p \approx 150$ to $200$ cm$^2$/(V$\cdot$s), requiring PMOS to be 2 to 3 times wider for equal drive current. Strain engineering has partially closed this gap: compressive SiGe source/drain boosts hole mobility 50 to 100 percent, while tensile SiN liners enhance electron mobility 10 to 30 percent.

The CMOS inverter transfer characteristic defines digital noise margins and switching behavior. The switching threshold $V_M = (V_{DD} + V_{th,n} + V_{th,p}\sqrt{\beta_n/\beta_p}) / (1 + \sqrt{\beta_n/\beta_p})$ is targeted at $V_{DD}/2$ for symmetric noise margins. The transfer curve passes through five regions as both transistors transition between linear, saturation, and off states, with the high-gain transition region setting noise margins $NM_H = V_{OH} - V_{IH}$ and $NM_L = V_{IL} - V_{OL}$.

Thermal noise in a MOSFET channel arises from random carrier scattering and sets the amplifier noise floor. The drain current noise PSD is $S_{id} = 4kT\gamma g_m$, where $\gamma = 2/3$ for long channels (potentially higher for short channels due to hot electrons). Van der Ziel first derived the expression; Scholten at NXP characterized short-channel enhancements for the PSP noise model. The input-referred noise $S_{vg} = 4kT\gamma/g_m$ decreases with increasing $g_m$, motivating large transistors at high current for low-noise front ends.

Flicker noise dominates at low frequencies and is critical for oscillator phase noise and sensor interfaces. The McWhorter number-fluctuation model gives $S_{id} = K_F g_m^2 / (C_{ox}^2 WL f)$, arising from carrier tunneling into oxide traps. The unified model from Hung, Ko, and Hu at Berkeley incorporates both number fluctuation and correlated mobility fluctuation: $S_{id} = (g_m^2 / (WLC_{ox}^2 f))(N_T / (1 + \alpha_s \mu_{eff} C_{ox} (Q_{inv}/q))^2)$. PMOS devices exhibit 5 to 10 times lower flicker noise than NMOS, which is why PMOS input pairs are preferred in low-noise amplifier design below the $1/f$ corner.

Random telegraph noise is the discrete manifestation of individual oxide traps capturing and emitting carriers. When gate area shrinks to $10^3$ nm$^2$ and below, single-trap events produce $\Delta I_D/I_D \approx g_m/(I_D \cdot C_{ox} WL) \cdot q$, large enough to cause SRAM bit errors or comparator uncertainty. RTN is statistically related to flicker noise: the $1/f$ spectrum arises from superposition of many RTN traps, with $\sigma(\Delta V_{th,RTN}) \propto 1/\sqrt{WL}$.

Process variation follows Pelgrom's law with threshold mismatch scaling as the inverse square root of gate area. Pelgrom's 1989 paper at Philips established $\sigma(\Delta V_{th}) = A_{VT}/\sqrt{WL}$, with $A_{VT} \approx 3$ to $4$ mV$\cdot\mu$m at 65 nm. For minimum-size devices ($W = 0.12$ $\mu$m, $L = 0.065$ $\mu$m), $\sigma(\Delta V_{th}) \approx 35$ to $45$ mV. The physical origin is Poisson fluctuation in the number of dopant atoms under the gate: only a few hundred atoms in the depletion region for minimum devices with $N_A = 5 \times 10^{18}$ cm$^{-3}$. FinFET processes with undoped channels ($N_A < 10^{16}$ cm$^{-3}$) improve $A_{VT}$ below 1 mV$\cdot\mu$m, shifting dominant variability to line-edge roughness, fin-width variation, and metal-gate work-function granularity.

The Pao-Sah double integral provides the most physically rigorous drain current by integrating carrier concentration over channel length and depth. The current $I_D = -(W\mu/L)\int_{2\phi_F+V_{SB}}^{2\phi_F+V_{DB}} Q_{inv}(\psi_s) d\psi_s$ requires iterative numerical solution of Poisson's equation, making it too expensive for SPICE but serving as the gold standard for compact model validation.

The Brews charge-sheet approximation simplifies Pao-Sah by treating the inversion layer as an infinitesimally thin charge sheet. This eliminates the depth integral, producing continuous current and conductance expressions that accurately capture the weak-to-strong inversion transition. It forms the theoretical basis for PSP, which parameterizes surface potential as a function of terminal voltages and derives charge and current from it, with all operating regions emerging naturally without region-stitching conditionals.

BSIM3 and BSIM4 from Berkeley are the most widely deployed compact models in commercial simulators. Developed under Chenming Hu and Cheng, BSIM4 uses a threshold-voltage-based core with smoothing functions for continuity, encompassing over 300 parameters covering short-channel effects, mobility degradation, gate tunneling, noise, stress, and well-proximity effects. Parameter extraction follows a bottom-up sequence: C-V on capacitors for $C_{ox}$ and $EOT$, long-channel transistors for $V_{th0}$, $\mu_0$, $K_1$, then short-channel devices for $DVT0$, $ETA0$, $PCLM$, $VSAT$, with temperature and noise characterization completing the set.

The PSP model from NXP and TU Delft solves for surface potential directly, providing inherently smooth derivatives. Rather than starting from threshold voltage, PSP uses an implicit equation from Gauss's law to find $\psi_s$ at source and drain ends, naturally capturing all inversion regimes without stitching. This derivative smoothness is critical for harmonic-balance and periodic-steady-state simulations in analog and RF design, and PSP was adopted as a CMC standard alongside BSIM4.

The EKV model provides a symmetric, charge-based framework built around the $g_m/I_D$ design methodology. Enz, Krummenacher, and Vittoz at EPFL expressed drain current as the difference of forward and reverse currents, each a function of a single inversion coefficient $i_f = I_F/I_{spec}$ where $I_{spec} = 2n\mu C_{ox}(W/L)V_T^2$. The interpolation function $i_f = (\ln(1 + \exp(v_p/2)))^2$ with $v_p = (V_{GS} - V_{th})/(nV_T)$ smoothly bridges weak ($i_f \ll 1$), moderate ($i_f \approx 1$), and strong ($i_f \gg 1$) inversion in a single equation.

[Terminal Voltages: V_GS, V_DS, V_BS]
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         v
[Compute surface potential psi_s (PSP) OR threshold voltage V_th (BSIM) OR inversion coefficient i_f (EKV)]
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         v
[Apply mobility model: mu_eff(E_eff, V_GS)]
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         v
[Compute drain current I_D with velocity saturation, CLM, DIBL corrections]
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         v
[Compute terminal charges Q_G, Q_S, Q_D, Q_B (Ward-Dutton partitioning)]
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         v
[Derive capacitances C_ij = dQ_i/dV_j and transconductances g_m, g_ds]
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         v
[Add noise sources: thermal (4kT gamma g_m), flicker (K_F/(C_ox^2 WL f)), RTN]
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         v
[Add parasitic elements: R_S, R_D, R_G, substrate network, NQS effects]
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         v
[Output to SPICE: I(V), Q(V), noise PSD for circuit simulation]

The BSIM-CMG model extends compact modeling to FinFET and gate-all-around nanosheet architectures. It uses surface-potential equations for thin-body double-gate or triple-gate structures, with $W_{fin}$ and $H_{fin}$ replacing planar width. Quantum confinement in narrow fins (5 to 7 nm at 7 nm node) shifts $V_{th}$ upward by 50 to 100 mV. The model includes self-heating (critical due to poor thermal paths through narrow fins), parasitic resistance in raised S/D epitaxy, and fin-edge roughness, and serves as the CMC standard for TSMC, Samsung, Intel, and GlobalFoundries FinFET PDKs.

Dennard scaling maintained constant electric fields as dimensions shrank, but its breakdown transformed device physics into circuit design constraints. Dennard at IBM proposed in 1974 that scaling dimensions and voltages by factor $\kappa$ keeps fields constant and improves speed by $\kappa$. This worked through the early 2000s, but $V_{th}$ scaling halted around 0.7 to 0.8 V because each 60 to 80 mV reduction increases $I_{off}$ by a decade. Multi-threshold libraries, power gating, DVFS, and the FinFET/GAA transition represent the industry's response.

The inversion charge centroid displacement from quantum confinement requires capacitance corrections. The wave function must vanish at the Si-SiO$_2$ interface, pushing the charge centroid 0.5 to 1.0 nm into silicon and adding an effective series capacitance $\epsilon_{si}/z_{avg}$. For $EOT = 0.8$ nm, this reduces $C_{gg}$ by 20 to 30 percent. The van Dort model and BSIM4 QM correction ($ADOS$, $BDOS$ parameters) capture this effect.

Substrate resistance networks model distributed RC coupling between the body terminal and intrinsic device at RF frequencies. Signals from the drain couple through junction capacitance and substrate resistance, degrading isolation and adding noise. Triple-well processes require networks including p-well resistance, n-well junction capacitance, and deep n-well resistance. Accurate substrate modeling is critical for LNA noise figure prediction, where coupling can degrade NF by 0.5 to 1.0 dB.

Non-quasi-static effects become significant when operating frequency approaches $f_T$, requiring distributed channel models. Above roughly $f_T/5$, finite carrier transit time introduces phase delays between gate voltage and channel charge. The Elmore-delay approximation adds effective gate resistance $R_{ch,NQS} \approx 1/(5g_m)$ in series with $C_{gs}$. BSIM4 and PSP include optional NQS sub-circuits at the cost of additional simulation overhead.

Temperature dependence pervades every MOSFET equation from threshold voltage to leakage current. $V_{th}$ decreases at $-1$ to $-2$ mV/K, mobility follows $\mu \propto T^{-1.5}$ to $T^{-2}$, and subthreshold current increases exponentially as $V_T = kT/q$ rises while $V_{th}$ falls. At $125$ $^\circ$C, leakage power can be 5 to 10 times higher than at $25$ $^\circ$C. The zero-temperature-coefficient bias point, where mobility and drive effects cancel, provides a useful reference for temperature-stable circuits.

Self-heating in FinFET and SOI devices creates electrothermal feedback that compact models must capture. Thermal resistance from channel to substrate reaches 10,000 to 50,000 K/W per fin, producing 20 to 50 K temperature rise at typical power levels. This reduces drain current by 5 to 15 percent and can introduce negative output conductance at high $V_{DS}$. Models use a single-pole $R_{th}$-$C_{th}$ thermal network feeding back into all temperature-dependent parameters.

Gate-induced drain leakage creates an off-state current through band-to-band tunneling at the gate-drain overlap. GIDL current $I_{GIDL} \propto \exp(-B_{GIDL}/(V_{DG}-V_{th,GIDL}))$ limits off-state leakage in low-power applications and is exacerbated by thin oxides and high drain voltages. In DRAM, GIDL at the access transistor is a primary retention limiter.

The unified current equation requires smoothing functions that avoid conditional branching in SPICE. Modern models use smooth functions like $V_{GST,eff} = V_T \cdot \ln(1 + \exp((V_{GS}-V_{th})/(nV_T)))$, which approaches $V_{GS}-V_{th}$ in strong inversion and $nV_T \exp((V_{GS}-V_{th})/(nV_T))$ in subthreshold. Similarly, an effective drain voltage $V_{DS,eff}$ uses hyperbolic smoothing to transition between linear ($V_{DS,eff} \approx V_{DS}$) and saturation ($V_{DS,eff} \approx V_{DS,sat}$) without discontinuities. The mathematical elegance masks considerable effort by Cheng and Hu to avoid unphysical artifacts in derivative quantities critical for distortion analysis.

The intrinsic gain $A_v = g_m/g_{ds}$ has eroded steadily with scaling, creating tension between digital speed and analog precision. At 180 nm, minimum-length NMOS achieves $A_v \approx 40$ to $60$ (32 to 36 dB); at 7 nm FinFET, only 5 to 10 (14 to 20 dB). The decline is driven by $g_{ds}$ increasing faster (shorter channels, stronger DIBL) than $g_m$ (which saturates from velocity saturation). Analog designers respond with longer channels, gain-boosting architectures, and digital calibration.

Stress-dependent mobility corrections account for intentional strain engineering in modern processes. Stress depends on layout context: active-area length, finger count, and contact proximity all affect local strain. BSIM4 captures this through $SA$, $SB$, $SD$ parameters measuring gate-to-STI distances, modifying mobility, $V_{th}$, and $v_{sat}$. The LOD (length-of-diffusion) effect causes 5 to 15 percent current variation between identical transistors in different layout contexts.

Well proximity effects from ion-implant scattering near well edges create systematic threshold voltage gradients. Scattered ions land 0.2 to 1.0 $\mu$m from the well boundary, raising local $V_{th}$ by 20 to 50 mV. BSIM4 models this through $SCA$, $SCB$, $SCC$ parameters extracted from device arrays at varying distances from well edges.

The gate current model separately treats direct tunneling, Fowler-Nordheim tunneling, and trap-assisted tunneling. BSIM4 partitions gate current into channel ($I_{gc}$) and overlap ($I_{gs}$, $I_{gd}$) components, each with separate parameter sets for accumulation and inversion regimes. With high-k dielectrics, trap-assisted tunneling through oxygen vacancies in HfO2 creates residual leakage modeled semi-empirically.

The $g_m/I_D$ design methodology unifies all inversion regimes into a single analog design space. At $g_m/I_D \approx 25$ V$^{-1}$ (weak inversion), current efficiency is maximized but speed is limited; at $g_m/I_D \approx 5$ V$^{-1}$ (strong inversion), speed is high but current is large. The moderate-inversion sweet spot around 10 to 15 V$^{-1}$ often provides the best compromise. EKV gives the closed form $g_m/I_D = (1/nV_T) \cdot 1/(0.5 + \sqrt{0.25 + i_f})$ for initial sizing.

The Gummel symmetry test validates that compact models produce symmetric behavior when source and drain are interchanged. Since the MOSFET is physically symmetric (ignoring halo implants), $I_D(V_{DS}) = -I_D(-V_{DS})$ and all even-order derivatives must vanish at $V_{DS} = 0$. Models failing this test produce kinks in $g_{ds}$ that corrupt distortion analysis. EKV satisfies symmetry by construction through its forward-minus-reverse formulation.

The BSIM-IMG model addresses FD-SOI physics where the back gate provides dynamic threshold voltage control. The ultrathin body (6 to 8 nm on 25 nm BOX) is fully depleted, eliminating body effect and random dopant fluctuation. Back-gate coupling through $C_{BOX} = \epsilon_{ox}/t_{BOX}$ enables approximately 80 to 100 mV/$V$ threshold tuning, supporting body-biased standard cells for dynamic power-performance trade-off without additional mask steps.

The evolution from planar to FinFET to GAA represents progression toward ideal electrostatic control. The natural length $\lambda_1 = \sqrt{\epsilon_{si} t_{ox} t_{si}/\epsilon_{ox}}$ for single-gate becomes $\lambda_2 = \sqrt{\epsilon_{si} t_{ox} t_{fin}/(2\epsilon_{ox})}$ for double-gate (FinFET) and $\lambda_{GAA} = \sqrt{\epsilon_{si} t_{ox} r/(2\epsilon_{ox})}$ for gate-all-around. The Taur-Ning criterion $L_{min} \approx 5\lambda$ to $7\lambda$ predicts FinFET limits at $L \approx 15$ to $21$ nm (consistent with 7 nm node) and GAA limits at $L \approx 10$ to $14$ nm (sufficient for 3 nm and 2 nm nodes). The complementary FET (CFET) stacks NMOS and PMOS vertically, requiring coupled thermal network modeling.

The noise figure of a MOSFET LNA depends on balancing thermal noise, gate-induced noise, and matching losses. The minimum noise figure $NF_{min} \approx 1 + (2/3)\sqrt{\gamma \delta(1 - |c|^2)} \cdot (f/f_T)$ shows that operating well below $f_T$ is essential. The gate resistance directly degrades $NF_{min}$, motivating multi-finger layout. FinFET processes at 7 nm achieve $NF_{min}$ below 0.5 dB at 28 GHz for 5G applications.

The complete noise model combines thermal, flicker, shot, and induced gate noise into a unified spectral density. The total PSD is $S_{id}(f) = 4kT\gamma g_m + K_F g_m^2/(C_{ox}^2 WL f) + 2qI_G$, with induced gate noise $S_{ig} = 4kT\delta\omega^2 C_{gs}^2/(5g_m)$ becoming relevant above $f_T/3$. The channel and gate noise are partially correlated with $|c_0| \approx 0.395$ for long channels, and this correlation must be included in optimum noise matching for LNA design.

Compact model convergence requires continuous equations and bounded derivatives across the entire voltage space. Kinks in $g_m$ or $g_{ds}$ from inadequate smoothing create Jacobian singularities that cause Newton-Raphson oscillation. BSIM4 and PSP have undergone decades of refinement targeting convergence in production-scale simulations with millions of transistor instances. The overlap and fringing capacitances become relatively more important below 50 nm gate length, where overlap constitutes 50 percent of total $C_{gs}$ in 12 nm FinFETs, and inner fringing through 5 to 8 nm spacers can rival overlap capacitance.

The small-signal model extends to large-signal transient analysis through the charge-based formulation. Terminal charges $Q_G$, $Q_D$, $Q_S$, $Q_B$ are computed as functions of all terminal voltages, with capacitive currents $I_{Ci} = dQ_i/dt$ ensuring charge conservation regardless of voltage swing amplitude. The small-signal capacitances $C_{ij} = \partial Q_i/\partial V_j$ emerge as the linearized version at the operating point.

Read MOSFET equations through a device-physics lens rather than a black-box-parameter lens.