MRAM (Magnetoresistive RAM) Fabrication is the semiconductor manufacturing process for producing non-volatile memory that stores data using magnetic tunnel junctions (MTJs) — where information is encoded as the relative magnetization direction of two ferromagnetic layers separated by a thin oxide barrier, offering unique combination of non-volatility, SRAM-like speed (~10 ns), unlimited endurance (>10¹⁵ cycles), and CMOS compatibility that makes embedded MRAM the leading replacement for embedded flash at advanced nodes.
MTJ Structure
``
[Top electrode (TaN/Ta)]
[Free layer (CoFeB ~1-2 nm)] ← Magnetization can switch
[MgO tunnel barrier (~1 nm)] ← Ultrathin insulator
[Reference layer (CoFeB)] ← Fixed magnetization
[SAF + pinning layers] ← Locks reference direction
[Bottom electrode (TaN/Ta)]
- Parallel magnetization (P): Low resistance (R_P) → Logic "0".
- Anti-parallel (AP): High resistance (R_AP) → Logic "1".
- TMR ratio: (R_AP - R_P) / R_P = 100-200% for CoFeB/MgO MTJ.
Switching Mechanisms
| Type | How It Switches | Speed | Energy | Maturity |
|------|----------------|-------|--------|----------|
| STT-MRAM | Spin-transfer torque from current through MTJ | 5-30 ns | ~100 fJ | Production |
| SOT-MRAM | Spin-orbit torque from adjacent heavy metal | 1-10 ns | ~10 fJ | R&D |
| VCMA-MRAM | Voltage-controlled magnetic anisotropy | <1 ns | ~10 fJ | Research |
STT-MRAM Write Process
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Write "1" (P → AP):
Current flows from free layer to reference layer
Spin-polarized electrons exert torque on free layer
Free layer magnetization flips to anti-parallel
Write "0" (AP → P):
Current flows in reverse direction
Spin torque flips free layer back to parallel
Read:
Small current measures resistance
R_high → AP → "1", R_low → P → "0"
`
MRAM Fabrication Process Flow
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[CMOS BEOL up to target metal layer]
↓
[Bottom electrode deposition (TaN/Ta PVD)]
↓
[MTJ film stack deposition (PVD/sputtering, ~20-30 layers, total ~20-30 nm)]
- Seed layer, SAF, reference CoFeB, MgO, free CoFeB, cap
- All deposited in ultra-high vacuum, <10⁻⁸ Torr
- MgO barrier must be precisely 1.0 ± 0.1 nm
↓
[Anneal (300-400°C in magnetic field) → crystallize CoFeB, set reference direction]
↓
[Patterning: Ion beam etch (IBE) or RIE to define MTJ pillars]
- Critical: No chemical attack on magnetic layers
- Redeposition of metallic material → shorts between layers
↓
[Encapsulation (SiN/SiO₂) to protect MTJ]
↓
[Continue BEOL: Via, upper metal layers]
Manufacturing Challenges
| Challenge | Why It's Hard | Solution |
|-----------|-------------|----------|
| MgO thickness control | ±0.1 nm needed across 300mm wafer | Advanced PVD control |
| MTJ patterning | No volatile etch products for Co/Fe | Ion beam etch (IBE) |
| Redeposition | Etched metal redeposits on MTJ sidewalls | Angled IBE, in-situ clean |
| CMOS thermal budget | MTJ degrades >400°C | Low-T BEOL after MTJ |
| Uniformity | TMR variation across wafer | Interface engineering |
MRAM vs. Other Memory
| Property | SRAM | DRAM | Flash | STT-MRAM |
|----------|------|------|-------|----------|
| Speed (read) | <1 ns | ~10 ns | ~25 µs | ~10 ns |
| Non-volatile | No | No | Yes | Yes |
| Endurance | Unlimited | Unlimited | 10⁴-10⁵ | >10¹⁵ |
| Density | Low (6T cell) | High (1T1C) | Very high | Medium (1T1MTJ) |
| Embedded at 5nm | Yes | No | No | Yes |
Production Status
- TSMC: Embedded MRAM at 22nm and 16nm for IoT/MCU products.
- Samsung: 28nm eMRAM in production.
- GlobalFoundries: 22FDX with eMRAM.
- Intel: Research on SOT-MRAM for cache replacement.
MRAM fabrication is the convergence of magnetic materials science and CMOS manufacturing — by integrating nanometer-thick magnetic tunnel junctions into standard BEOL process flows, MRAM brings non-volatile, high-speed, unlimited-endurance memory to advanced logic chips, enabling instant-on processors, non-volatile caches, and persistent computing architectures that fundamentally change how systems handle power and data persistence.