Multi-Corner Multi-Mode (MCMM) Timing Signoff is the comprehensive static timing analysis methodology that simultaneously verifies chip timing correctness across all combinations of process-voltage-temperature (PVT) corners and functional operating modes, ensuring that setup and hold timing constraints are met under every condition the chip may encounter during its operational lifetime — the definitive timing verification step that determines whether a design can be taped out.

PVT Corners:

• Process Corners: represent manufacturing variation extremes; SS (slow-slow: both NMOS and PMOS slow), FF (fast-fast), TT (typical-typical), SF (slow NMOS/fast PMOS), FS (fast NMOS/slow PMOS); SS corners determine maximum delay (setup critical), FF corners determine minimum delay (hold critical)
• Voltage Corners: supply voltage varies due to regulation tolerance and IR drop; typical VDD ± 10% for core logic; low voltage produces slower gates (setup critical) while high voltage produces faster gates (hold critical)
• Temperature Corners: operating temperature range (e.g., -40°C to 125°C for automotive); at older nodes, high temperature is slow (normal temperature inversion); at advanced FinFET nodes below ~16 nm, temperature inversion means low temperature can be the slow corner for certain paths
• Corner Count: the full matrix of process × voltage × temperature creates dozens to hundreds of corners; practical MCMM analysis selects 8-20 representative corners that capture worst-case timing for both setup and hold

Operating Modes:

• Functional Modes: different chip configurations (mission mode, test mode, debug mode) activate different clock frequencies, power domains, and signal paths; timing must be met independently in each mode
• Power States: DVFS operating points define different voltage-frequency combinations; each operating point represents a separate mode that must be timing-clean; transitions between power states must also be verified
• Clock Configurations: multiple clock domains may operate at different frequencies in different modes; inter-clock-domain paths require separate timing constraints for each mode-specific frequency relationship

On-Chip Variation (OCV):

• Flat OCV Derate: applies a uniform derating factor (e.g., ±5%) to all cell delays to model local variation between launch and capture paths; simple but overly pessimistic, leading to over-design
• AOCV (Advanced OCV): derating depends on logic depth and physical distance; paths with more stages experience averaging of random variation, resulting in smaller effective derating; AOCV tables provided by the foundry specify derating factors indexed by stage count and distance
• POCV (Parametric OCV): models delay variation statistically with per-cell sigma values; provides the most accurate representation of local variation with the least pessimism; enables statistical analysis that can recover 5-15% timing margin compared to flat OCV
• SOCV (Statistical OCV): combines POCV cell-level statistics with spatial correlation models to accurately predict the probability of timing failure; enables yield-aware timing signoff where designs target a specific yield percentage rather than absolute worst-case corners

Signoff Flow:

• Constraint Specification: SDC (Synopsys Design Constraints) files define clocks, generated clocks, input/output delays, false paths, and multi-cycle paths for each mode; constraint quality directly determines the accuracy and efficiency of timing analysis
• Multi-Scenario Analysis: EDA tools (Synopsys PrimeTime, Cadence Tempus) simultaneously analyze all corner-mode combinations; each scenario identifies its worst-violating paths, and the designer optimizes accordingly
• ECO Fixing: engineering change orders insert buffers, resize gates, swap cells, or reroute nets to fix remaining violations; the challenge is fixing violations in one scenario without creating new violations in other scenarios

MCMM timing signoff is the comprehensive verification discipline that guarantees chip functionality across all manufacturing variations and operating conditions — the ultimate quality gate for digital design that directly determines silicon success or failure on first tape-out.