3D NAND Flash Scaling encompasses the technology for manufacturing vertically stacked flash memory cells — now exceeding 200 layers — where charge-trap flash cells are formed along vertical channels etched through alternating oxide/nitride or oxide/poly layers delivering exponentially increasing bit density per die area without requiring the extreme lithographic resolution that limited planar NAND scaling.
From 2D to 3D NAND:
``
Planar NAND hit fundamental limits at ~15nm half-pitch:
- Cell-to-cell interference (capacitive coupling)
- Too few electrons per cell (unreliable storage)
- Extreme lithography cost for small features
3D NAND solution: stack cells vertically
Instead of shrinking horizontally → build taller
Feature sizes RELAX to ~30-40nm (vertical pitch)
Density increase from stacking more layers
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3D NAND Architecture:
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Cross-section of 3D NAND:
─── Metal bitline ───
│
┌────┴────┐
Layer 200+ │ WL 200 │ ← Wordline (gate)
│ WL 199 │
│ ... │
│ WL 2 │
│ WL 1 │ ← Each WL = one cell
└────┬────┘
│
─── Source line ───
Vertical channel (poly-Si, ~50-80nm diameter)
Surrounding each channel:
Tunnel oxide (SiO₂) │ Charge trap (Si₃N₄) │ Blocking oxide │ WL metal
Key Technologies:
- High-aspect-ratio etch: Etching memory holes through 200+ layers of alternating oxide/nitride stack. AR exceeds 60:1 at the most advanced nodes. The deepest etches in semiconductor manufacturing (~10-15μm deep, 50-80nm diameter holes).
- Channel formation: Deposit thin poly-Si film lining the memory hole → forms the transistor channel. Must be continuous and uniform through the full stack height.
- Charge trap flash: Si₃N₄ trapping layer (instead of floating gate) stores charge. Electrons tunnel from channel through thin SiO₂ into Si₃N₄. Advantage: more tolerant of cell-to-cell variation than floating gate.
- Gate replacement (TCAT process): Samsung's approach — deposit O/N stack, etch holes + channels, then replace the nitride with tungsten metal gates through access slits.
- Metal gate: Tungsten (W) deposited by CVD fills the thin gate regions between oxide layers. ALD TiN is used as barrier/adhesion.
Scaling Generations:
| Generation | Layers | Vendors | Key Innovation |
|-----------|--------|---------|----------------|
| 1st gen | 24-32L | ~2013-2015 | Basic 3D concept proven |
| 4th gen | 96-128L | ~2019-2020 | String stacking (two stacks bonded) |
| 6th gen | 176L | ~2021 | CMOS-under-array (CuA) |
| 8th gen | 232-236L | ~2023 | Double-stack bonding |
| 9th gen | 280-321L | 2024-2025 | Triple-stack, >300 layers |
| Future | 400-500L | 2026+ | Quad-stack, molybdenum gates |
String Stacking: Instead of etching through the full stack at once (impossible at >200 layers), process the stack in 2-3 segments, each ~100 layers, and bond them using inter-stack connection vias. This relaxes the AR requirement for each individual etch.
CMOS-under-Array (CuA): Place peripheral logic (page buffer, decoder, control) underneath the memory array instead of beside it, dramatically reducing die area. Enabled by wafer-to-wafer bonding: fabricate CMOS logic wafer → fabricate memory array wafer → bond face-to-face.
QLC/PLC Multi-Level:
| Level | Bits/Cell | Levels | Endurance |
|-------|----------|--------|----------|
| SLC | 1 | 2 | 100K cycles |
| MLC | 2 | 4 | 10K cycles |
| TLC | 3 | 8 | 1-3K cycles |
| QLC | 4 | 16 | 500-1K cycles |
| PLC | 5 | 32 | ~100 cycles |
3D NAND is the most successful semiconductor scaling strategy of the past decade — by decoupling density scaling from lithographic resolution and instead scaling vertically, the NAND industry has continued to deliver exponential capacity growth, enabling the data-intensive AI era with ever-cheaper, denser solid-state storage.