Gate-All-Around (GAA) nanosheet transistor is the device architecture that succeeds FinFET at the 3 nm node and below — a stack of horizontal silicon nanosheets where the gate electrode wraps all four sides of each channel, delivering the tightest electrostatic control physically possible in a planar-compatible flow. TSMC calls it N2 (2025), Intel calls it RibbonFET / Intel 20A (2024), and Samsung calls it 3GAE / MBCFET (2022 risk). The architecture solves FinFET's fundamental scaling wall: once the fin is too narrow to conduct useful current, the only path forward is stacking multiple wider sheets and gating them from every direction.

Why FinFET ran out of road. A FinFET gates three sides of a tall, narrow fin. As gate length shrinks below ~12 nm, the fin must get narrower to maintain short-channel control — but carrier mobility in a sub-5 nm fin collapses due to surface roughness and quantum confinement. GAA sidesteps this by using wider sheets (30–50 nm) that are thin vertically (5–7 nm) and fully surrounded — electrostatic control improves while drive current scales with sheet width × number of stacked sheets.

Electrostatic advantage — the natural length. The quality of gate control is captured by the natural length $\lambda$. For a rectangular nanosheet gated on all four sides:

$$\lambda_{\text{GAA}} = \sqrt{\frac{\varepsilon_{\text{si}}}{\varepsilon_{\text{ox}}} \cdot \frac{t_{\text{si}} \cdot t_{\text{ox}}}{4}}$$

Compare FinFET (three-sided gate):

$$\lambda_{\text{FinFET}} = \sqrt{\frac{\varepsilon_{\text{si}}}{\varepsilon_{\text{ox}}} \cdot \frac{t_{\text{si}} \cdot t_{\text{ox}}}{3}}$$

The factor of 4 vs 3 in the denominator gives GAA a ~15 % shorter natural length at the same body thickness — which directly translates to less DIBL, steeper subthreshold swing, and lower leakage at matched gate length.

The nanosheet stack — a superlattice epitaxy. Fabrication begins with alternating epitaxial Si/SiGe layers grown on the substrate: 3–4 pairs of SiGe₀.₃ sacrificial layers (5–8 nm) interleaved with Si channel layers (5–7 nm). Total stack height: 40–60 nm. Thickness uniformity must hold to <0.1 nm across the wafer because any variation propagates into threshold-voltage mismatch across billions of transistors.

Inner spacer — the module that didn't exist in FinFET. After dummy-gate patterning and source/drain cavity etch, the SiGe sacrificial layers are selectively recessed laterally (2–5 nm pullback) with a vapor-phase HCl or dry isotropic etch. Low-k dielectric (SiOCN or SiCO, $k \approx$ 4–5) fills the cavities and is etched back, leaving inner spacers that isolate the gate from the source/drain epitaxy. These spacers define the parasitic gate-to-S/D capacitance — the single largest contributor to AC performance loss at advanced nodes.

Channel release — the defining GAA etch. After removing the dummy gate, a highly selective isotropic etch removes the SiGe sacrificial layers while leaving the Si nanosheets intact. Selectivity requirement: >100:1 (SiGe:Si). The released sheets are then cleaned and prepared for high-k/metal-gate (HKMG) deposition, which wraps conformally around all four sides of each sheet.

Drive-current scaling — width × stacks. Unlike FinFET where current scales only by adding more fins (at a fixed narrow width), GAA lets designers tune two independent knobs:

Backside power delivery (BSPDN). At 2 nm and below, the metal interconnect stack above the transistors is so dense that routing power rails on the frontside wastes ~20 % of the standard-cell area. GAA at N2/20A pairs with backside power delivery — power (VDD/VSS) rails are fabricated on the wafer backside after wafer thinning, connected to the transistors through nano-TSVs. This recovers routing tracks for signals and shrinks cell height by 1–2 tracks.

Thermal and reliability. Stacking 3–4 channels inside a ~60 nm pillar concentrates heat. Self-heating in the inner sheets (farther from the substrate heat sink) is 10–30% worse than FinFET at the same power density. Mitigation: thinner SiGe (wider thermal path between sheets after release), metal gate fill optimization, and backside cooling pathways through the nano-TSVs. Reliability shifts from fin-corner TDDB (FinFET) to sheet-edge gate-oxide stress — the tight inner curvature concentrates the electric field.

<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 700 480" font-family="system-ui,sans-serif">
  <!-- background -->
  <rect width="700" height="480" fill="#1a1a17" rx="12"/>
  <text x="350" y="32" fill="#c9c3f2" font-size="16" text-anchor="middle" font-weight="600">GAA nanosheet transistor — cross-section (gate-cut view)</text>

  <!-- substrate -->
  <rect x="50" y="400" width="600" height="60" fill="#2a2a28" stroke="#6f6f6a" stroke-width="1"/>
  <text x="350" y="438" fill="#8a8a86" font-size="13" text-anchor="middle">Si substrate</text>

  <!-- STI -->
  <rect x="50" y="360" width="150" height="40" fill="#3a3a37" stroke="#6f6f6a" stroke-width="1"/>
  <rect x="500" y="360" width="150" height="40" fill="#3a3a37" stroke="#6f6f6a" stroke-width="1"/>
  <text x="125" y="385" fill="#8a8a86" font-size="11" text-anchor="middle">STI</text>
  <text x="575" y="385" fill="#8a8a86" font-size="11" text-anchor="middle">STI</text>

  <!-- source/drain epi blocks -->
  <rect x="150" y="200" width="80" height="200" fill="#4a7a4a" stroke="#6fbf6f" stroke-width="1.5" rx="3"/>
  <text x="190" y="310" fill="#bff0bf" font-size="12" text-anchor="middle" transform="rotate(-90 190 310)">Source (SiGe:B epi)</text>

  <rect x="470" y="200" width="80" height="200" fill="#4a7a4a" stroke="#6fbf6f" stroke-width="1.5" rx="3"/>
  <text x="510" y="310" fill="#bff0bf" font-size="12" text-anchor="middle" transform="rotate(-90 510 310)">Drain (SiGe:B epi)</text>

  <!-- gate metal wrapping nanosheets -->
  <!-- sheet 1 (bottom) -->
  <rect x="230" y="340" width="240" height="40" fill="#5a4a8a" stroke="#9a8adf" stroke-width="1.2" rx="4"/>
  <!-- Si channel inside -->
  <rect x="245" y="352" width="210" height="16" fill="#e8d44d" stroke="#c9b030" stroke-width="1" rx="2"/>

  <!-- sheet 2 (middle) -->
  <rect x="230" y="270" width="240" height="40" fill="#5a4a8a" stroke="#9a8adf" stroke-width="1.2" rx="4"/>
  <rect x="245" y="282" width="210" height="16" fill="#e8d44d" stroke="#c9b030" stroke-width="1" rx="2"/>

  <!-- sheet 3 (top) -->
  <rect x="230" y="200" width="240" height="40" fill="#5a4a8a" stroke="#9a8adf" stroke-width="1.2" rx="4"/>
  <rect x="245" y="212" width="210" height="16" fill="#e8d44d" stroke="#c9b030" stroke-width="1" rx="2"/>

  <!-- inner spacers -->
  <rect x="230" y="244" width="12" height="22" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>
  <rect x="458" y="244" width="12" height="22" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>
  <rect x="230" y="314" width="12" height="22" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>
  <rect x="458" y="314" width="12" height="22" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>
  <rect x="230" y="384" width="12" height="16" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>
  <rect x="458" y="384" width="12" height="16" fill="#3a6a6a" stroke="#6fafaf" stroke-width="0.8" rx="2"/>

  <!-- gate contact on top -->
  <rect x="310" y="170" width="80" height="28" fill="#5a4a8a" stroke="#9a8adf" stroke-width="1.5" rx="3"/>
  <text x="350" y="189" fill="#d4c8ff" font-size="11" text-anchor="middle">Gate metal</text>

  <!-- labels with leader lines -->
  <!-- Si channel label -->
  <line x1="460" y1="220" x2="530" y2="160" stroke="#c9b030" stroke-width="0.8"/>
  <text x="535" y="155" fill="#e8d44d" font-size="12">Si nanosheet (5–7 nm)</text>
  <text x="535" y="170" fill="#8a8a86" font-size="11">channel, W = 30–50 nm</text>

  <!-- gate wrap label -->
  <line x1="240" y1="225" x2="80" y2="160" stroke="#9a8adf" stroke-width="0.8"/>
  <text x="55" y="148" fill="#c9c3f2" font-size="12">HK/MG gate wrap</text>
  <text x="55" y="163" fill="#8a8a86" font-size="11">(all 4 sides)</text>

  <!-- inner spacer label -->
  <line x1="236" y1="255" x2="80" y2="260" stroke="#6fafaf" stroke-width="0.8"/>
  <text x="55" y="255" fill="#6fafaf" font-size="11">Inner spacer</text>
  <text x="55" y="270" fill="#8a8a86" font-size="10">(SiOCN, k≈4.5)</text>

  <!-- dimension arrows -->
  <!-- stack height -->
  <line x1="490" y1="200" x2="490" y2="400" stroke="#8a8a86" stroke-width="0.8" stroke-dasharray="3,2"/>
  <text x="495" y="305" fill="#8a8a86" font-size="10" transform="rotate(90 495 305)">stack ≈ 50–60 nm</text>

  <!-- title: 3 stacked sheets -->
  <text x="350" y="462" fill="#8a8a86" font-size="12" text-anchor="middle">3 stacked nanosheets — gate wraps all 4 sides of each channel</text>
</svg>

Process complexity and cost. GAA adds ~15–20 % more mask layers than FinFET at the same node: inner spacer etch/dep, selective SiGe release, multi-threshold work-function-metal patterning inside the tight gate-all-around cavity, and (at N2) backside lithography. Wafer cost at N2 is estimated at $25,000–$30,000 per 300 mm wafer (vs $16,000–$20,000 for N3 FinFET) — a cost that only AI-accelerator and high-end SoC volumes can absorb.

The road ahead — CFET. Beyond 4–5 stacked sheets, the next architectural step is CFET (complementary FET): the NMOS nanosheet stack is placed directly above (or below) the PMOS stack within the same standard-cell footprint, cutting cell area roughly in half. CFET is projected for the Å-scale nodes (TSMC A14, Intel 14A, ~2028–2030) and requires sequential or monolithic 3D integration — bonding or growing two active device layers with aligned contacts between them.