Nanosheet SiGe/Si Superlattice is the epitaxially grown alternating stack of thin SiGe and Si layers that forms the starting material for gate-all-around (GAA) nanosheet transistors — where selective removal of the SiGe sacrificial layers releases the Si nanosheets that become the transistor channels, with stack quality directly determining device performance and yield.
Superlattice Structure
- Typical stack: 3-5 pairs of alternating SiGe/Si layers on Si substrate.
- Each layer: 5-12 nm thick — precisely controlled by epitaxial growth.
- Example (3nm node): SiGe(8nm)/Si(6nm)/SiGe(8nm)/Si(6nm)/SiGe(8nm)/Si(6nm)/SiGe(8nm).
- Bottom SiGe layer acts as isolation from substrate.
Epitaxial Growth Requirements
| Parameter | Specification | Impact |
|---|---|---|
| Si thickness uniformity | ± 0.3 nm across wafer | Vt variation |
| SiGe thickness uniformity | ± 0.5 nm across wafer | Release etch selectivity |
| Ge composition (25-30%) | ± 1% across wafer | Etch selectivity to Si |
| Interface sharpness | < 1 nm transition | Carrier scattering |
| Defect density | < 0.1/cm² | Yield |
Growth Process
- RPCVD (Reduced Pressure Chemical Vapor Deposition): Standard tool for superlattice growth.
- Temperature: 500-700°C.
- Precursors: SiH2Cl2 (DCS) for Si, GeH4 + SiH2Cl2 for SiGe.
- Pressure: 10-50 Torr.
- Growth Rate: ~1-5 nm/min — slow for thickness control.
- In-Situ Doping: B2H6 or PH3 added for n-well/p-well doping during growth.
Channel Release Process
1. Fin patterning: Superlattice stack etched into fin shape. 2. Dummy gate formation: Covers channel region. 3. Source/drain etch and epi: Lateral SiGe layers exposed. 4. Inner spacer formation: Etch lateral SiGe recess near gate, fill with dielectric. 5. SiGe sacrificial removal: Selective vapor-phase or wet etch removes all SiGe layers.
- Chemistry: Peracetic acid or vapor HCl — etches SiGe > 100:1 selectivity to Si.
6. Gate wrap-around: High-k/metal gate deposited around released Si nanosheets.
Stacking Variants
- 3 nanosheets: Current production (Samsung 3nm, Intel 20A).
- 4 nanosheets: Planned for next generation — more drive current per footprint.
- CFET (Complementary FET): NMOS nanosheet stack on top of PMOS stack — ultimate density.
The SiGe/Si superlattice is the foundation of the GAA nanosheet transistor era — epitaxial growth quality at the angstrom level directly controls the threshold voltage uniformity, drive current, and yield of every nanosheet transistor fabricated at 3nm and beyond.
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