Nanosheet Transistor Fabrication is the manufacturing process for creating horizontally-oriented, vertically-stacked silicon channel sheets with gate-all-around geometry — requiring precise epitaxial growth of Si/SiGe superlattices, selective sacrificial layer removal, and conformal gate stack deposition to achieve the electrostatic control and drive current density required for 3nm and 2nm technology nodes.

Superlattice Epitaxy:

• Growth Conditions: reduced-pressure CVD (RP-CVD) or ultra-high vacuum CVD (UHV-CVD) at 550-650°C; SiH₄ or Si₂H₆ precursor for Si layers; GeH₄ added for SiGe layers; growth rate 0.5-2 nm/min for thickness control; chamber pressure 1-20 Torr
• Layer Thickness Control: Si channel layers 5-7nm thick (final nanosheet thickness); SiGe sacrificial layers 10-12nm thick (determines vertical spacing after release); thickness uniformity <3% (1σ) across 300mm wafer required; in-situ ellipsometry monitors growth in real-time
• Ge Composition: SiGe layers contain 25-40% Ge; higher Ge content improves etch selectivity (Si:SiGe >100:1) but increases lattice mismatch and defect density; composition uniformity <2% required; strain management critical to prevent dislocation formation
• Stack Architecture: typical 3-sheet stack: substrate / SiGe (12nm) / Si (6nm) / SiGe (12nm) / Si (6nm) / SiGe (12nm) / Si (6nm) / SiGe cap (5nm); total height ~80nm; 2nm node uses 4-5 sheets with reduced spacing (8-10nm SiGe layers)

Fin and Gate Patterning:

• EUV Lithography: 0.33 NA EUV scanner (ASML NXE:3400) patterns fins at 24-30nm pitch; single EUV exposure replaces 193i SAQP for cost and overlay improvement; photoresist (metal-oxide or chemically amplified) 20-30nm thick; dose 40-60 mJ/cm²
• Fin Etch: anisotropic plasma etch (Cl₂/HBr/O₂ chemistry) transfers pattern through Si/SiGe stack; etch selectivity to hard mask (TiN or SiON) >20:1; sidewall angle 88-90° for vertical fin profiles; etch stop on buried oxide (BOX) or Si substrate
• Dummy Gate Stack: poly-Si deposited by LPCVD at 600°C, 50-80nm thick; gate patterning by EUV lithography; gate length 12-16nm (physical), 10-12nm (electrical after spacer and recess); gate pitch 48-54nm at 3nm node
• Spacer Formation: conformal SiN deposition by ALD or PECVD, 4-6nm thick; anisotropic etch leaves spacers on gate sidewalls; spacer width 6-8nm determines S/D-to-gate separation; low-k spacer (SiOCN, k~4.5) reduces parasitic capacitance by 15-20%

Source/Drain Engineering:

• S/D Recess Etch: anisotropic etch removes Si/SiGe stack in S/D regions; etch stops at bottom Si sheet or substrate; recess depth 60-100nm; creates cavity for epitaxial S/D growth; sidewall profile controlled to prevent spacer damage
• Epitaxial S/D Growth: NMOS uses SiP (Si:P) grown at 650-700°C with PH₃ doping, P concentration 1-3×10²¹ cm⁻³; PMOS uses SiGe:B grown at 550-600°C with B₂H₆ doping, B concentration 1-2×10²¹ cm⁻³, Ge 30-40% for strain; diamond-shaped faceted growth merges between fins
• Contact Resistance: silicide formation (NiPtSi or TiSi) at S/D-metal interface; contact resistivity <1×10⁻⁹ Ω·cm² required; S/D contact pitch 20-24nm; contact via resistance <100Ω per contact; metal fill (W or Co) by CVD
• Strain Engineering: SiGe:B S/D induces compressive strain in PMOS channel (10-20% hole mobility enhancement); tensile strain for NMOS from SiP S/D or contact etch stop layer (CESL) provides 5-10% electron mobility boost

Nanosheet Release Process:

• Dummy Gate Removal: CMP planarization followed by selective poly-Si etch; gate trench opened exposing Si/SiGe stack edges; trench width 12-16nm; etch chemistry (SF₆/O₂ plasma or TMAH wet etch) selective to ILD and spacer
• Selective SiGe Etch: vapor-phase HCl etch at 600-700°C (isotropic, selectivity >100:1) or wet etch using H₂O₂:HF mixture (room temperature, selectivity 50-100:1); etch rate 5-20 nm/min; etch time 30-90 seconds removes 10-12nm SiGe laterally from each side
• Suspended Nanosheet Formation: Si sheets remain suspended with 10-12nm vertical gaps; nanosheet width 15-40nm (lithographically defined); length equals gate length (12-16nm); mechanical stability maintained by S/D anchors; no sagging or collapse due to high Si stiffness
• Cleaning and Passivation: dilute HF dip removes native oxide; ozone or plasma oxidation grows 0.5-0.8nm chemical oxide for interface quality; H₂ anneal at 800°C for 60 seconds passivates dangling bonds; surface roughness <0.3nm RMS required

Gate Stack Deposition:

• Conformal HfO₂ ALD: precursor (TDMAH or TEMAH) and oxidant (H₂O or O₃) pulsed alternately at 250-300°C; 20-30 ALD cycles deposit 2-3nm HfO₂; conformality >95% (top:bottom:sidewall thickness ratio); wraps all four sides of each nanosheet plus top and bottom surfaces
• Work Function Metal: TiN (4.5-4.7 eV) for PMOS, TiAlC or TaN (4.2-4.4 eV) for NMOS deposited by ALD; 2-4nm thick; composition tuned for multi-Vt options; conformality >90% required to maintain Vt uniformity across nanosheet stack
• Gate Fill Metal: W deposited by CVD (WF₆ + H₂ at 400°C) or Co by ALD/CVD; fills remaining gate trench volume; low resistivity (W: 10-15 μΩ·cm, Co: 15-20 μΩ·cm); void-free fill critical for reliability; CMP planarizes to ILD level
• Post-Deposition Anneal: 900-1000°C spike anneal in N₂ for 5-30 seconds; crystallizes HfO₂ (monoclinic phase); activates S/D dopants; forms abrupt S/D junctions; reduces interface trap density to <5×10¹⁰ cm⁻²eV⁻¹

Nanosheet transistor fabrication is the most complex and precise semiconductor manufacturing process ever deployed in high-volume production — requiring atomic-level control of epitaxial growth, nanometer-scale selective etching, and conformal deposition on 3D suspended structures to create the transistors that power 3nm and 2nm chips with billions of devices per square centimeter.